Abstract: The present invention relates to a polyethylene composition comprising a base resin comprising a low molecular weight ethylene polymer component and a high molecular weight ethylene polymer component, wherein the high molecular weight ethylene polymer component has a higher weight average molecular weight than the low molecular weight ethylene polymer component, wherein the base resin has a density of at least 958.0 kg/m3, and the polyethylene composition a melt flow rate MFR2 (190° C., 2.16 kg) of from 0.50 to 0.80 g/10 min and a molecular weight distribution being the ratio of the weight average molecular weight and the number average molecular weight, Mw/Mn, of from 10.0 to 15.0, a process for producing said polyethylene composition, an article comprising said polyethylene composition and the use of said polyethylene composition for the production of a film.

Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.

Abstract: A microprocessor which comprises a three input adder, a two input adder, apparatus for providing the components of a virtual address to the first and second adders on a first clock period, and apparatus for providing a segment base address to the first adder on the first clock period, apparatus for determining the type of addresses generated by the adders on a second clock period and for generating an output address on the second clock period, and apparatus for determining access violations during a third clock period.

Abstract: A microprocessor which comprises a three input adder, a two input adder, apparatus for providing the components of a virtual address to the first and second adders on a first clock period, and apparatus for providing a segment base address to the first adder on the first clock period, apparatus for determining the type of addresses generated by the adders on a second clock period and for generating an output address on the second clock period, and apparatus for determining access violations during a third clock period.