Patents by Inventor Ashish Gadagkar

Ashish Gadagkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6243781
    Abstract: In a bus resource having an outbound pipe for processing both non-posted and posted transactions in a FIFO manner, a rejected non-posted transaction at the head of the outbound pipe is moved aside and into an auxiliary buffer to avoid a potential blockage of the outbound pipe. The auxiliary buffer is for holding transaction information and return data of the rejected non-posted transaction. The rejected transaction is eventually completed from the auxiliary buffer as determined by an arbiter.
    Type: Grant
    Filed: December 3, 1998
    Date of Patent: June 5, 2001
    Assignee: Intel Corporation
    Inventors: Wishwesh Gandhi, Tuong Trieu, Ashish Gadagkar, Zohar Bogin, David D. Lent
  • Patent number: 6237055
    Abstract: An arbiter comprising logic circuitry configured to delay granting bus ownership to an agent X in response to receiving a first signal which indicates that a device coupled to the bus is not available to service transactions directed at the device over the bus. For instance, the device may be a bridge and the grant is delayed if an inbound pipe of the bridge is full. The arbiter may provide a borrowed grant to an outbound pipe of the device for performing a transaction on the bus while waiting for an inbound pipe of the device to become available.
    Type: Grant
    Filed: December 3, 1998
    Date of Patent: May 22, 2001
    Assignee: Intel Corporation
    Inventors: Tuong Trieu, David D. Lent, Zohar Bogin, Ashish Gadagkar
  • Patent number: 6202112
    Abstract: An embodiment of the invention is directed at a bridge having an outbound pipe for buffering transaction information and data being transported from various devices to a bus. The bridge has an arbiter for granting requests associated with these devices to access the outbound pipe for transferring the transaction information and data into the pipe. The bridge generates a reject signal in response to an initial request associated with an initial transaction from a first one of the devices if the outbound pipe is unavailable to accept further transaction information or data. The bridge has response control logic for generating a retry response for the initial transaction in response to the reject signal. The bridge is able to assert a stamp signal in response to the reject signal. The arbiter in response to the stamp being asserted waits, without granting any other lower priority requests to access the outbound pipe, until a subsequent transaction from the first device makes progress.
    Type: Grant
    Filed: December 3, 1998
    Date of Patent: March 13, 2001
    Assignee: Intel Corporation
    Inventors: Ashish Gadagkar, Zohar Bogin, Narendra Khandekar, David D. Lent