Patents by Inventor Ashish Ghai

Ashish Ghai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180373644
    Abstract: Apparatuses, systems, methods, and computer program products are disclosed for multi-plane memory management. An apparatus includes a failure detection circuit that detects a failure of a storage element during an operation. An apparatus includes a test circuit that performs a test on a storage element. An apparatus includes a recycle circuit that enables a portion of a storage element for use in operations in response to the portion of the storage element passing a test.
    Type: Application
    Filed: June 26, 2017
    Publication date: December 27, 2018
    Applicant: Western Digital Technologies, Inc.
    Inventors: Daniel Joseph Linnen, Ashish Ghai, Dongxiang Liao, Srikar Peesari, Avinash Rajagiri, Philip Reusswig, Bin Wu
  • Publication number: 20180061505
    Abstract: Technology is described herein for detecting a leakage current between a block select line and a conductive region that exists in multiple blocks of memory cells in a plane. The conductive region may be shared by at least one memory cell in multiple blocks. One example of the conductive region is a common source line that includes one or more local source lines and one or more global source lines. If the leakage current were to become high enough, the electrical short between the conductive region and the block select line could cause a plane level failure. If the leakage current is less than an amount that would cause a plane failure, but that indicates that the non-volatile memory device is susceptible to a plane failure, data may be moved out of the plane before the plane failure occurs. Thus, data loss may be prevented.
    Type: Application
    Filed: August 24, 2016
    Publication date: March 1, 2018
    Applicant: SanDisk Technologies LLC
    Inventors: Ashish Ghai, Lakshmi Kalpana Vakati, Ekamdeep Singh, Chang Siau, Gopinath Balakrishnan, Kapil Verma
  • Patent number: 9905307
    Abstract: Technology is described herein for detecting a leakage current between a block select line and a conductive region that exists in multiple blocks of memory cells in a plane. The conductive region may be shared by at least one memory cell in multiple blocks. One example of the conductive region is a common source line that includes one or more local source lines and one or more global source lines. If the leakage current were to become high enough, the electrical short between the conductive region and the block select line could cause a plane level failure. If the leakage current is less than an amount that would cause a plane failure, but that indicates that the non-volatile memory device is susceptible to a plane failure, data may be moved out of the plane before the plane failure occurs. Thus, data loss may be prevented.
    Type: Grant
    Filed: August 24, 2016
    Date of Patent: February 27, 2018
    Assignee: SanDisk Technologies LLC
    Inventors: Ashish Ghai, Lakshmi Kalpana Vakati, Ekamdeep Singh, Chang Siau, Gopinath Balakrishnan, Kapil Verma
  • Patent number: 9711227
    Abstract: To prevent data loss due to latent defects, a non-volatile memory system will use a leakage detection circuit to test for small amounts of leakage that indicate that the memory is susceptible to failure.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: July 18, 2017
    Assignee: SanDisk Technologies LLC
    Inventors: Ashish Ghai, Yuvaraj Krishnamoorthy, Ekamdeep Singh, Kalpana Vakati, Maythin Uthayopas, Mark Shlick, Srikar Peesari
  • Patent number: 8953398
    Abstract: A system for grading blocks may be used to improve memory usage. Blocks of memory, such as on a flash card, may be graded on a sliding scale that may identify a level of “goodness” or a level of “badness” for each block rather than a binary good or bad identification. This grading system may utilize at least three tiers of grades which may improve efficiency by better utilizing each block based on the individual grades for each block. The block leveling grading system may be used for optimizing the competing needs of minimizing yield loss while minimizing testing defect escapes.
    Type: Grant
    Filed: June 19, 2012
    Date of Patent: February 10, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Dana Lee, Jianmin Huang, Mrinal Kochar, Ashish Ghai
  • Publication number: 20130336059
    Abstract: A system for grading blocks may be used to improve memory usage. Blocks of memory, such as on a flash card, may be graded on a sliding scale that may identify a level of “goodness” or a level of “badness” for each block rather than a binary good or bad identification. This grading system may utilize at least three tiers of grades which may improve efficiency by better utilizing each block based on the individual grades for each block. The block leveling grading system may be used for optimizing the competing needs of minimizing yield loss while minimizing testing defect escapes.
    Type: Application
    Filed: June 19, 2012
    Publication date: December 19, 2013
    Applicant: SANDISK TECHNOLOGIES INC.
    Inventors: Dana Lee, Jianmin Huang, Mrinal Kochar, Ashish Ghai