Patents by Inventor Ashish Goel

Ashish Goel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120089681
    Abstract: A system and a method are disclosed for recommending electronic messages in a message sharing system. Users can post messages to the message sharing system. These messages from posting users are received by the system and sent to receiving users that have subscribed to the posting users. The receiving users interact with the messages in various ways, such as by sharing the messages with other users. Interaction information is received for each of the electronic messages. The interaction information includes an indication of the number of interactions with the electronic message by receiving users. A score is determined for each electronic message based on the interaction information. Electronic messages are selected for being recommended to a user or a group of users based on the scores. The recommendations are then sent to the users, enabling users to better focus their attention on messages that are likely to be interesting.
    Type: Application
    Filed: October 6, 2010
    Publication date: April 12, 2012
    Applicant: TWITTER, INC.
    Inventors: Abdur Chowdhury, Ashish Goel, Ram Ravichandran
  • Publication number: 20110292292
    Abstract: A method of displaying consecutively first and second asynchronous video data streams on a display device, where there is a transition from the first video data stream to the second video data stream. The transition includes interrupting updating the display on the video display device during a prolonged vertical blanking interval in response to assertion of a vertical blanking pulse in the first video stream until subsequent de-assertion of a vertical blanking pulse in the second video stream, and displaying the second video data stream starting with a frame following the subsequent de-assertion of the vertical blanking pulse in the second video stream.
    Type: Application
    Filed: May 25, 2010
    Publication date: December 1, 2011
    Applicant: FREESCALE SEMICONDUCTOR, INC
    Inventors: Ashish GOEL, Kshitij Bajaj, Vandana Bansal, Ankit Gupta, Gurinder Singh
  • Publication number: 20110212518
    Abstract: A process for high expression of protein of interest using an expression vector. The process comprises at least the following regulatory elements: a) a CMV promoter, or its functional variants, b) an intron, c) TPL or its functional variants, d) VA genes or functional variants, and e) a bovine growth hormone polyadenylation sequence or functional variants.
    Type: Application
    Filed: June 19, 2006
    Publication date: September 1, 2011
    Applicant: CADILA HEALTHCARE LIMITED
    Inventors: Arun K. Singh, Ashish Goel, Sanjeev K. Mendiratta
  • Patent number: 7952401
    Abstract: A standby control circuit for an integrated circuit module includes a first control circuit that is responsive, in a normal operating mode of the integrated circuit module, to an asynchronous standby signal indicating a standby mode entry event to output a standby mode signal synchronous with a primary clock signal to indicate a standby operating mode of the integrated circuit module. The standby control circuit also includes a second control circuit which is responsive, in a reduced power mode of the integrated circuit module, to the asynchronous standby signal indicating the standby mode entry event to control the first control circuit to output the standby mode signal synchronous with a secondary clock signal to indicate the standby operating mode.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: May 31, 2011
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Shankar Ramakrishnan, Kumar Abhishek, Ashish Goel, Ankit Gupta, Chandan Gupta, Mithlesh Shrivas, Rahul Sood
  • Publication number: 20100102865
    Abstract: A standby control circuit for an integrated circuit module includes a first control circuit that is responsive, in a normal operating mode of the integrated circuit module, to an asynchronous standby signal indicating a standby mode entry event to output a standby mode signal synchronous with a primary clock signal to indicate a standby operating mode of the integrated circuit module. The standby control circuit also includes a second control circuit which is responsive, in a reduced power mode of the integrated circuit module, to the asynchronous standby signal indicating the standby mode entry event to control the first control circuit to output the standby mode signal synchronous with a secondary clock signal to indicate the standby operating mode.
    Type: Application
    Filed: September 24, 2009
    Publication date: April 29, 2010
    Applicant: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Shankar RAMAKRISHNAN, Kumar ABHISHEK, Ashish GOEL, Ankit GUPTA, Chandan GUPTA, Mithlesh SHRIVAS, Rahul SOOD
  • Publication number: 20060255833
    Abstract: A FPGA device that includes a plurality of programmable logic blocks connected to each other through interconnect resources, one or more sets of registers connected to the interconnect resources for configuring the programmable logic blocks. Additional logic is provided with the registers for selecting an interconnect/logic block testing mode thereby enabling a rapid interconnect/logic testing.
    Type: Application
    Filed: December 5, 2005
    Publication date: November 16, 2006
    Applicant: STMicroelectronics Pvt. Ltd.
    Inventors: Pramod Singh, Ashish Goel
  • Publication number: 20060022700
    Abstract: An improved digital circuit for reducing readback time in field programmable gate arrays (FPGAs) includes a shift register having a plurality of latches and a clock and a reset signal provided to the latches. An interconnect circuit is provided between each pair of latches of the shift register for providing a selective data frame from the desired latch or latches. Connecting a control signal generator to a control input of said interconnect circuit enables quick readback of selected data frames, thereby reducing the time consumed for debugging of an FPGA.
    Type: Application
    Filed: July 26, 2005
    Publication date: February 2, 2006
    Inventors: Ashish Goel, Davinder Aggarwal
  • Publication number: 20050172070
    Abstract: An improved programmable logic device provides increased efficiency and enhanced flexibility in configuration of block memories and includes one or more memory blocks and a vertical shift register that receives the data to be loaded in the memory blocks. The PLD further provides a selection device for selecting the memory cells in the memory blocks that are to store the received data, and a control block for controlling the loading of the data in the memory blocks. The selection device includes an address counter connected to the input of an address decoder so as to enable the selection of addresses in the memory blocks.
    Type: Application
    Filed: December 6, 2004
    Publication date: August 4, 2005
    Applicant: STMicroelectronics Pvt. Ltd.
    Inventors: Davinder Aggarwal, Ashish Goel, Namerita Khanna
  • Publication number: 20050127943
    Abstract: A Programmable Logic Device provides efficient scalability for configuration memory programming while requiring reduced area for implementation. The device includes an array of configuration memory cells, a Vertical Shift Register (VSR) connected to the vertical lines of the array of configuration memory cells, a Select Register (SR) connected to the horizontal lines of the array of configuration memory cells, a Horizontal Shift Register (HSR) providing the enable input to the Select Register (SR), and a Configuration State Machine (CSM) which synchronizes the operations of the VSR, SR and HSR.
    Type: Application
    Filed: September 30, 2004
    Publication date: June 16, 2005
    Applicant: STMicroelectronics PVT. LTD.
    Inventors: Ashish Goel, Davinder Aggarwal
  • Patent number: 6816746
    Abstract: A method, system and logic are described for monitoring resources within a manufacturing environment. A system for monitoring resources within a manufacturing facility includes a remote monitoring system coupled to one or more pieces of equipment within the manufacturing facility. The remote monitoring system may be communicatively coupled to a control center operable to display status information associated with using the one or more pieces of equipment, and a simulator communicatively coupled to the remote monitoring system is operable to dynamically simulate resource re-allocation based on the inoperability of the one or more pieces of equipment.
    Type: Grant
    Filed: March 5, 2001
    Date of Patent: November 9, 2004
    Assignee: Dell Products L.P.
    Inventors: Branden Clark Bickley, Ashish Goel
  • Patent number: 6661797
    Abstract: Arrangements and methods for efficiently selecting an optimum connection path that meets user specified delay requirements with enhanced efficiency. In a basic aspect, a method is implemented by one of a plurality of algorithms to meet user QoS specifications. The user not only specifies a delay threshold T for the incoming request but also specifies a delay threshold tolerance &egr; for the path delay that will satisfy him. Two implementations are disclosed. The first is termed non-iterative and sets scaling factor &tgr;=min (T, (n−1)/&egr;), where n is a number of links in a shortest path, scales all the relevant delay parameters by &tgr;/T, truncates all the scaled values to integers, and uses a dynamic programming algorithm to accumulate the total of resulting link delay parameters values for each possible shortest path. The second method, termed iterative, is similar, except that it sets &tgr;<<T.
    Type: Grant
    Filed: February 28, 2000
    Date of Patent: December 9, 2003
    Assignee: Lucent Technologies Inc.
    Inventors: Ashish Goel, Deepak Kataria, Dimitris Logothetis, Kajamalai Gopalaswamy Ramakrishnan
  • Patent number: 6611727
    Abstract: A method, a system, and logic for simulating production within a build to order manufacturing environment are described. According to one aspect, a system for allocating resources within the manufacturing environment is disclosed. The system includes a control center operably coupled to one or more databases having associated work in process profile information for selective portions of a manufacturing facility. A simulator may be communicatively coupled to the control center to simulate allocation of resources based on real-time acquisition of information associated with the WIP information.
    Type: Grant
    Filed: March 5, 2001
    Date of Patent: August 26, 2003
    Assignee: Dell Products L.P.
    Inventors: Branden Clark Bickley, Ashish Goel
  • Publication number: 20020123813
    Abstract: A method, system and logic are described for monitoring resources within a manufacturing environment. A system for monitoring resources within a manufacturing facility includes a remote monitoring system coupled to one or more pieces of equipment within the manufacturing facility. The remote monitoring system may be communicatively coupled to a control center operable to display status information associated with using the one or more pieces of equipment.
    Type: Application
    Filed: March 5, 2001
    Publication date: September 5, 2002
    Applicant: DELL PRODUCTS L.P.
    Inventors: Branden C. Bickley, Ashish Goel
  • Publication number: 20020123815
    Abstract: In accordance with teachings of the present disclosure, a method, system and logic are described for simulating production within a build to order manufacturing environment. According to one aspect, a system for allocating resources within the manufacturing environment is disclosed. The system includes a control center operably coupled to one or more databases having associated work in process profile information for selective portions of a manufacturing facility. A simulator may be communicatively coupled to the control center to simulate allocation of resources based on real-time acquisition of information associated with the WIP information.
    Type: Application
    Filed: March 5, 2001
    Publication date: September 5, 2002
    Applicant: DELL PRODUCTS L.P.
    Inventors: Branden C. Bickley, Ashish Goel