Abstract: A computer implemented method of dynamically verifying clock domain crossing (CDC) paths in a register-transfer level (RTL) design is provided. In addition to static analysis, formal analysis, and simulation steps, each CDC path is allocated a persistent unique identifier. This enables the updating of a centralized results database using the persistent unique identifier to label the associated CDC protocol assertions, functional coverage, and results of the formal analysis and simulation. In addition, prior to simulation analysis, CDC protocol assertions that have been proven during formal analysis are turned off, resulting in the simulation run only being carried out for non-proven CDC protocol assertions.

Abstract: This application discloses a computing system to perform one or more static checks on clock domain crossings in a circuit design to detect combinational logic configured to generate output signals having glitches that cross clock domains in a circuit design. The computing system can identify the combinational logic is configured to generate the output signal based, at least in part, on an input signal and an inversion of the input signal. The computing system can identify conditions that, when satisfied, allow the combinational logic to generate the output signal based, at least in part, on the input signal and the inversion of the input signal, and generate a glitch expression based, at least in part, on the identified conditions. The computing system can determine the combinational logic is configured to generate at least one glitch in the output signal based, at least in part, on the glitch expression.

Abstract: Techniques are disclosed herein for reactively identifying software products, available from an electronic marketplace, that are exhibiting anomalous behavior. Data associated with software products is accessed and analyzed to determine anomalous behavior. The data analyzed may include, but is not limited to, crash data, ratings data, marketplace data, usage data, and the like. A machine learning mechanism may be used to classify the application into a category relating to whether a potential anomaly is identified for the software product. A score may also be calculated for the software applications that indicates a severity of the anomalous behavior. The classification and/or the score may be used to determine whether to perform further analysis or testing with regard to a software product. For instance, the score may be used to determine that the software product is to be tested by a testing service.

Abstract: This application discloses a computing system to perform one or more static checks on clock domain crossings in a circuit design to detect combinational logic configured to generate output signals having glitches that cross clock domains in a circuit design. The computing system can identify the combinational logic is configured to generate the output signal based, at least in part, on an input signal and an inversion of the input signal. The computing system can identify conditions that, when satisfied, allow the combinational logic to generate the output signal based, at least in part, on the input signal and the inversion of the input signal, and generate a glitch expression based, at least in part, on the identified conditions. The computing system can determine the combinational logic is configured to generate at least one glitch in the output signal based, at least in part, on the glitch expression.

Abstract: First-in-first-out (FIFO) structures are recognized and verified in integrated circuit (IC) designs. The FIFO recognition is based on structural analysis of the design. Specifically, the structural analysis includes performing seed based recognition by identifying logic elements that indicate the existence of candidate FIFO circuitry and then exploring the candidate circuitry to completely verify the presence of a FIFO structure. Recognized FIFOs may be verified to ensure the proper generation of the full and empty flags.

Abstract: First-in-first-out (FIFO) structures are recognized and verified in integrated circuit (IC) designs. The FIFO recognition is based on structural analysis of the design. Specifically, the structural analysis includes performing seed based recognition by identifying logic elements that indicate the existence of candidate FIFO circuitry and then exploring the candidate circuitry to completely verify the presence of a FIFO structure. Recognized FIFOs may be verified to ensure the proper generation of the full and empty flags.

Abstract: A structural analysis tool automatically detects complex handshake mechanisms for controlling data transfers between clock-domain crossings. The structural analysis tool may also verify the correctness of the handshake mechanism.