Patents by Inventor Ashish Jain

Ashish Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160331019
    Abstract: A leaf removal assembly including a frame comprising a front plate having a feed opening, a leaf stripping assembly mounted on said front plate in front of said feed opening and an upper sprocket wheel comprising a plurality of upper socket grippers extending radially outward of the upper sprocket wheel and being disposed behind the front plate. The leaf removal assembly further includes a lower sprocket wheel comprising a plurality of lower sprocket grippers extending radially outwardly of the lower sprocket wheel and being disposed behind the front plate. At least one of the upper sprocket wheel and the lower sprocket wheel may be adjustably attached to the frame. A process for separating a leaf from a stalk comprising at least one leaf is also included.
    Type: Application
    Filed: March 31, 2016
    Publication date: November 17, 2016
    Inventors: James David Evans, Ashish Jain, Loren Theodore Duvekot, David C. Haller
  • Patent number: 9477289
    Abstract: A system has a plurality of electronic components including a memory, a PHY coupled to the memory, and one or more other electronic components. Power consumed by the PHY is estimated during operation of the system. Estimating the power consumed by the PHY includes modeling the power consumed by the PHY as a linear function with respect to memory bandwidth. Available power for the PHY is determined based at least in part on the estimated power consumed by the PHY. At least a portion of the available power for the PHY is allocated to at least one of the one or more other components.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: October 25, 2016
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: Ashish Jain, Alexander J. Branover, Guhan Krishnan
  • Publication number: 20160306406
    Abstract: A power management controller tracks the idle state of a compute unit and compares the tracked idle state with a first threshold. If the tracked idle state is above the first threshold a power state of the compute unit is limited to a low power state so that the power state does not rise due to activity that occurs in low utilization scenarios. The tracked idle state is compared to a second threshold and if the tracked idle state is below the second threshold, indicating that the compute unit is not in a low utilization scenario, a limit on the power state is removed and the power state of the compute unit is allowed to rise.
    Type: Application
    Filed: September 4, 2015
    Publication date: October 20, 2016
    Inventors: Alexander J. Branover, Adam N.C. Clark, Ashish Jain, Sridhar V. Gada
  • Publication number: 20160283379
    Abstract: Methods and structure for utilizing linked lists to flush a cache. One exemplary embodiment includes a memory, an interface, and an Input/Output (I/O) processor. The memory implements a cache divided into cache lines, and the interface receives I/O directed to a block address of a storage device. The I/O processor determines a remainder by dividing the block address by the number of cache lines, and selects a cache line for storing the I/O based on the remainder. The I/O processor determines a quotient by dividing the block address by the number of cache lines, and associates the quotient with the selected cache line. Additionally, the I/O processor populates a linked list by inserting entries that each point to a different cache line associated with the same quotient, and flushes the cache lines to the storage device in block address order by traversing the entries of the linked list.
    Type: Application
    Filed: March 27, 2015
    Publication date: September 29, 2016
    Inventors: Sumanesh Samanta, Horia Cristian Simionescu, Ashish Jain
  • Publication number: 20160266628
    Abstract: A method includes controlling a power limit of a computing system based on a determined skin temperature of at least one location on an outer surface of a device housing the computing system. A processor includes a processing unit and a power management controller to control a power limit of the processing unit based on a determined skin temperature of at least one location on an outer surface of a device housing the processor.
    Type: Application
    Filed: March 9, 2015
    Publication date: September 15, 2016
    Inventors: Ashish Jain, Benjamin David Bates, Ali Akbar Merrikh, Samuel David Naffziger, Steven Frederick Liepe, Madhu Saravana Sibi Govindan
  • Publication number: 20160266629
    Abstract: A method includes adjusting a maximum skin temperature threshold of a device based on a device state, adjusting a power limit for the device based on the adjusted maximum skin temperature threshold, and operating the device based on the adjusted power limit. A processor includes a processing unit and a power management controller to adjust a maximum skin temperature threshold based on a device state and adjust a power limit for the processing unit based on the adjusted maximum skin temperature threshold.
    Type: Application
    Filed: March 9, 2015
    Publication date: September 15, 2016
    Inventors: Ali Akbar Merrikh, Ashish Jain, Benjamin David Bates, Yasuko Eckert, Indrani Paul, Wei Huang, Manish Arora, Alexander Joseph Branover, Sridhar V. Gada, Andrew McNamara, Samuel David Naffziger, Steven Frederick Liepe, Madhu Saravana Sibi Govindan
  • Patent number: 9384135
    Abstract: The disclosure is directed to a system and method of cache management for a data storage system. According to various embodiments, the cache management system includes a hinting driver and a priority controller. The hinting driver generates pointers based upon data packets intercepted from data transfer requests being processed by a host controller of the data storage system. The priority controller determines whether the data packets are associated with at least a first (high) priority level or a second (normal or low) priority level based upon the pointers generated by the hinting driver. High priority data packets are stored in cache memory regardless of whether they satisfy a threshold heat quotient (i.e. a selected level of data transfer activity).
    Type: Grant
    Filed: September 4, 2013
    Date of Patent: July 5, 2016
    Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.
    Inventors: Vineet Agarwal, Ashish Jain, Amit Kumar Sharma
  • Patent number: 9298243
    Abstract: The present application describes embodiments of a method that includes modifying an operating point of at least one of a memory physical layer interface or a memory controller in response to changes in bandwidth utilization of the memory physical layer interface. The present application also describes embodiments of an apparatus that includes a memory controller, a memory physical layer interface, and a power management controller to modify an operating point of at least one of the memory physical layer interface or the memory controller in response to changes in bandwidth utilization of the memory physical layer interface.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: March 29, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Ashish Jain, Alexander J. Branover
  • Patent number: 9261949
    Abstract: An apparatus and method for dynamically adjusting power limits for processing nodes and other components, such as peripheral interfaces, is disclosed. The apparatus includes multiple processing nodes and other components, and further includes a power management unit configured to set a first frequency limit for at least one of the processing nodes responsive to receiving an indication of a first detected temperature greater than a first temperature threshold. Initial power limits are set below guard-band power limits for components that do not have reliable reporting of power consumption or for cost or power saving reasons. The amount of throttling of processing nodes is used to adjust the power limits for the processing nodes and these components.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: February 16, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexander J. Branover, Ashish Jain, Ann M. Ling, Maurice B. Steinman
  • Patent number: 9261935
    Abstract: A method is provided for allocating power to compute units based on energy efficiency. Some embodiments of the method include allocating portions of a power budget of a system-on-a-chip (SOC) to a plurality of compute units implemented on the SOC based on ratios of a performance level for each compute unit to a power consumed by the compute unit operating at the performance level. An SOC is provided that includes a plurality of compute units and a power management controller to allocate portions of a power budget of the SOC to the plurality of compute units based on ratios of a performance level for each compute unit to a power consumed by the compute unit operating at the performance level.
    Type: Grant
    Filed: July 1, 2013
    Date of Patent: February 16, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Alexander J. Branover, Ashish Jain
  • Publication number: 20150277521
    Abstract: A system has a plurality of electronic components including a memory, a PHY coupled to the memory, and one or more other electronic components. Power consumed by the PHY is estimated during operation of the system. Estimating the power consumed by the PHY includes modeling the power consumed by the PHY as a linear function with respect to memory bandwidth. Available power for the PHY is determined based at least in part on the estimated power consumed by the PHY. At least a portion of the available power for the PHY is allocated to at least one of the one or more other components.
    Type: Application
    Filed: March 25, 2014
    Publication date: October 1, 2015
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Ashish Jain, Alexander J. Branover, Guhan Krishnan
  • Publication number: 20150268713
    Abstract: The operating point of a processing unit is controlled based on the power consumption (i.e., the rate of energy consumption) associated with a workload, wherein low power consumption may indicate short-duration workloads with idle phases and high power consumption may indicate long, sustained workloads. Energy credits are accumulated while a drain rate of a battery is lower than a threshold drain rate and the energy credits are consumed while the drain rate is higher than the threshold drain rate. The operating point of the processing unit may be increased from a first operating point to a second operating point in response to the energy credits exceeding a first threshold. The operating point of the processing unit may be decreased from the second operating point to the first operating point in response to the energy credits falling below a second threshold.
    Type: Application
    Filed: March 24, 2014
    Publication date: September 24, 2015
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Ashish Jain, Alexander J. Branover, Samuel D. Naffziger, Dongyuan Zhan
  • Publication number: 20150193259
    Abstract: A processing system detects user activities on one or more processing units. In response, an operating point (operating frequency or an operating voltage) of the processing unit handing the user activity is increased at the processing unit. Battery power may be conserved in some processing systems by limiting the increase in the operating point to a time interval and reducing the operating frequency or the operating voltage to a previous value after the time interval has elapsed.
    Type: Application
    Filed: January 3, 2014
    Publication date: July 9, 2015
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Ashish Jain, Alexander J. Branover
  • Patent number: 9053036
    Abstract: Aspects of the disclosure pertain to a system and method for providing a flash memory cache input/output throttling mechanism based upon temperature parameters for promoting improved flash life. The mechanism restricts flash memory cache caching of inputs/outputs associated with Least Recently Used data and Most Recently Used data when a temperature of the flash memory is at or above a threshold temperature.
    Type: Grant
    Filed: November 26, 2012
    Date of Patent: June 9, 2015
    Assignee: Avago Technologies General IP (Singapore) Pte Ltd
    Inventors: Ashish Jain, Kiran B. Dalvi, Amit K. Sharma
  • Publication number: 20150142661
    Abstract: Systems and methods are provided for managing shared expenses. The systems and methods may include a financial service provider identifying shared expenses in a customer's transaction history with software application executed on a server or personal computing device. The financial service provider may identify other individuals with whom the customer shares the expense, and send requests for reimbursement on the customer's behalf. The financial service provider may monitor the status of reimbursement payments, and send reminders as necessary until the shared expense has been reimbursed.
    Type: Application
    Filed: November 19, 2014
    Publication date: May 21, 2015
    Applicant: CAPITAL ONE FINANCIAL CORPORATION
    Inventors: Ashish JAIN, Vishal PURI, David DAO, Gagan KANJLIA
  • Patent number: 9003058
    Abstract: Method, User equipment, system and program for limiting an amount of information transmitted between a plurality of user equipments and a server. The method comprising establishing communication links between a plurality of user equipments based upon a proximity of the plurality of user equipments, determining a tactical common mission group selected from the linked plurality of user equipments using a mission profile stored in each of the plurality of user equipments; and selecting a proxy for the tactical common mission group. The proxy communicates with a server on behalf of the tactical common mission group. A proxy is selected based upon a ranking.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: April 7, 2015
    Assignee: Telcordia Technologies, Inc.
    Inventors: Chit Chung, Ashish Jain, Dennis Egan, John R. Wullert, II, Hyong Sop Shim
  • Publication number: 20150073611
    Abstract: An operating point of one or more components in a processing device may be set using a leakage current estimated based on at least one of a rate of temperature overages or a rate of power overages. In some embodiments, a power management controller may be used to set an operating point of one or more components in the processing device based on at least one of a rate of temperature overages or a rate of power overages for the component(s).
    Type: Application
    Filed: September 9, 2013
    Publication date: March 12, 2015
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Ashish Jain, Alexander J. Branover
  • Patent number: 8977853
    Abstract: The invention disclosed here is aimed at enabling a trusted third party to manage user opt-ins which would enable growth of personalized information services, that is, enabling trusted business relationships between three types of entities—an end-user, an information source/provider, and an application service provider/developer—so that they can have a controlled, secure and private exchange of sensitive and/or confidential information. The inventive system has modes of operation recommended based on various conditions, enabling a secure exchange of private information between personal information repository owners and application services providers to enable deliver of personalized services. One mode is Durable Subscription Management, which is used when per transaction approval is not needed, that is, when an end-user has given permission to access data for a given or predefined period of time.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: March 10, 2015
    Assignee: Telcordia Technologies, Inc.
    Inventors: Devasis Bassu, Ashish Jain, Shoshana Loeb, Stan Moyer, Thimios Panagos
  • Publication number: 20150039832
    Abstract: The disclosure is directed to a system and method of cache management for a data storage system. According to various embodiments, the cache management system includes a hinting driver and a priority controller. The hinting driver generates pointers based upon data packets intercepted from data transfer requests being processed by a host controller of the data storage system. The priority controller determines whether the data packets are associated with at least a first (high) priority level or a second (normal or low) priority level based upon the pointers generated by the hinting driver. High priority data packets are stored in cache memory regardless of whether they satisfy a threshold heat quotient (i.e. a selected level of data transfer activity).
    Type: Application
    Filed: September 4, 2013
    Publication date: February 5, 2015
    Applicant: LSI Corporation
    Inventors: Vineet Agarwal, Ashish Jain, Amit Kumar Sharma
  • Publication number: 20150006924
    Abstract: The present application describes embodiments of a method that includes modifying an operating point of at least one of a memory physical layer interface or a memory controller in response to changes in bandwidth utilization of the memory physical layer interface. The present application also describes embodiments of an apparatus that includes a memory controller, a memory physical layer interface, and a power management controller to modify an operating point of at least one of the memory physical layer interface or the memory controller in response to changes in bandwidth utilization of the memory physical layer interface.
    Type: Application
    Filed: July 1, 2013
    Publication date: January 1, 2015
    Inventors: Ashish Jain, Alexander J. Branover