Patents by Inventor Ashish James

Ashish James has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11953999
    Abstract: A technique provides efficient data failover by creation and deployment of a protection policy that ensures maintenance of frequent common snapshots between sites of a multi-site data replication environment. A global constraint optimizer executes on a node of a cluster to create the protection policy for deployment among other nodes of clusters at the sites. Constraints such as protection rules (PRs) specifying, e.g., an amount of tolerable data loss are applied to a category of data designated for failover from a primary site over a network to a plurality of (secondary and tertiary) sites typically located at geographically separated distances. The optimizer processes the PRs to compute parameters such as frequency of snapshot generation and replication among the sites, as well as retention of the latest common snapshot maintained at each site to create a recovery point and configuration of the protection policy that reduces network traffic for efficient use of the network among the sites.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: April 9, 2024
    Assignee: Nutanix, Inc.
    Inventors: Ashish Kumar, Freddy James, Kai Tan, Pranab Patnaik
  • Patent number: 11934801
    Abstract: Embodiments use a multi-modal approach to generate software programs that match a solution program description. The solution program description may include natural language, input-output examples, partial source code, desired operators, or other hints. Some embodiments use optimized prompts to a pre-trained language model to obtain initial candidate programs. Maximal program components are extracted and then recombined variously using component-based synthesis. Beam search reduces a solution program search space by discarding some candidates from a given synthesis iteration. Relevance metrics, string similarity metrics, operator frequency distributions, token rareness scores, and other optimizations may be employed. By virtue of optimizations and the multi-modal approach, a solution program may be obtained after fewer iterations than by use of a language model alone.
    Type: Grant
    Filed: December 7, 2021
    Date of Patent: March 19, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Kiarash Rahmani, Mohammad Raza, Sumit Gulwani, Vu Minh Le, Daniel James Morris, Arjun Radhakrishna, Gustavo Araujo Soares, Ashish Tiwari
  • Publication number: 20220004900
    Abstract: There is provided a method of predicting performance in electronic design based on machine learning using at least one processor, the method including: providing a first machine learning model configured to predict performance data for an electronic system based on a set of input design parameters for the electronic system; providing a second machine learning model configured to generate a new set of parameter values for the set of input design parameters for the electronic system based on a desired performance data provided for the electronic system; generating, using the second machine learning model, the new set of parameter values for the set of input design parameters for the electronic system based on the desired performance data provided for the electronic system; evaluating the set of input design parameters having the new set of parameter values for the electronic system to obtain an evaluated performance data associated with the set of input design parameters having the new set of parameter values;
    Type: Application
    Filed: November 25, 2019
    Publication date: January 6, 2022
    Inventors: Raju Salahuddin, Rahul Dutta, Kevin Tshun Chuan Chai, Ashish James, Chuan Sheng Foo, Zeng Zeng, Savitha Ramasamy, Vijay Ramaseshan Chandrasekhar
  • Publication number: 20180102792
    Abstract: According to various embodiments, a joint detector/decoder device may be provided. The joint detector/decoder device may include: an input circuit configured to receive an input signal; a splitting determination circuit configured to determine whether a survivor is to be split based on a parity check criterion; and a survivor splitting circuit configured to produce a plurality of survivors of a next instance based on at least one survivor of a previous instance and based on the input signal, if it is determined that the survivor of the previous instance is to be split; wherein each survivor has an associated bit sequence.
    Type: Application
    Filed: May 5, 2016
    Publication date: April 12, 2018
    Inventors: Kheong Sann Chan, Ashish James