Abstract: Described herein are improved techniques for measuring propagation delay of an integrated circuit that facilitate performing propagation delay measurements on-chip. Some embodiments relate to an integrated circuit comprising programmable oscillator circuitry with a plurality of oscillator stages that are switchable into and out of a delay path based on control signals from a controller, allowing the same programmable oscillator to generate many different oscillator signals according to the received control signals, for the controller to determine a central tendency and/or variance of propagation delay of the integrated circuit. Some embodiments relate to an integrated circuit including programmable delay paths configured to provide an amount of cell delay and an amount of wire delay based on control signals from a controller, allowing the same programmable delay path to generate signals for measuring delays due to cell and wire delays of the integrated circuit.

Abstract: An integrated circuit includes a programmable delay path comprising a plurality of path delay tuners configured to receive a plurality of control signals and add to the programmable delay path an amount of cell delay and an amount of wire delay that are based on the plurality of control signals. The integrated circuit further includes a controller configured to provide the plurality of control signals to the programmable delay path, receive a signal from the programmable delay path, and compare the signal to a reference signal.

Abstract: A voltage scaling system can include an oscillator, a power management unit, a frequency meter, a table unit and a control unit. The oscillator is used to generate a clock signal according to a code and a power signal. The power management unit is used to generate the power signal according to a first control signal corresponding to a requested voltage. The frequency meter is used to measure a frequency of the clock signal and generate a second control signal accordingly. The table unit is used to generate a minimum code. The control unit is used to generate the code and the first control signal according to the second control signal, the minimum code and a target frequency.

Abstract: A multicycle path circuit capable of operating at a functional mode and an at-speed test mode. The multicycle path circuit includes an on-chip controller configured to receive an on-chip clock signal and modulate the on-chip clock signal to provide a first clock signal to a first circuit and a second clock signal to a second circuit. The first clock signal and the second clock signal are in a multicycle phase relationship. The on-chip controller is configured to ensure the clock paths to and from the second circuit to be the same for the functional mode and the at-speed test mode and therefore to avoid hold and setup timing conflict between these modes.

Abstract: Described herein are improved techniques for measuring propagation delay of an integrated circuit that facilitate performing propagation delay measurements on-chip. Some embodiments relate to an integrated circuit comprising programmable oscillator circuitry with a plurality of oscillator stages that are switchable into and out of a delay path based on control signals from a controller, allowing the same programmable oscillator to generate many different oscillator signals according to the received control signals, for the controller to determine a central tendency and/or variance of propagation delay of the integrated circuit. Some embodiments relate to an integrated circuit including programmable delay paths configured to provide an amount of cell delay and an amount of wire delay based on control signals from a controller, allowing the same programmable delay path to generate signals for measuring delays due to cell and wire delays of the integrated circuit.

Abstract: Clock circuits designed to compensate for supply voltage fluctuations (e.g., supply voltage droops) in central processing units (CPUs) are described. The clock circuits described herein involve reducing the clock frequency in response to a decrease to the supply voltage to a value that is approximately equal (or below) to the maximum operating frequency of the CPU at that particular supply voltage. The clock circuits described herein may include a frequency locked loops (FLL). Such FLLs may be designed to lock to a reference frequency when the supply voltage is approximately constant and to deviate from the reference frequency in response to variations in the supply voltage. In some embodiments, an FLL operates in the same supply voltage domain as the CPU.

Abstract: Described herein are improved techniques for measuring propagation delay of an integrated circuit that facilitate performing propagation delay measurements on-chip. Some embodiments relate to an integrated circuit comprising programmable oscillator circuitry with a plurality of oscillator stages that are switchable into and out of a delay path based on control signals from a controller, allowing the same programmable oscillator to generate many different oscillator signals according to the received control signals, for the controller to determine a central tendency and/or variance of propagation delay of the integrated circuit. Some embodiments relate to an integrated circuit including programmable delay paths configured to provide an amount of cell delay and an amount of wire delay based on control signals from a controller, allowing the same programmable delay path to generate signals for measuring delays due to cell and wire delays of the integrated circuit.

Abstract: A multicycle path circuit capable of operating at a functional mode and an at-speed test mode. The multicycle path circuit includes an on-chip controller configured to receive an on-chip clock signal and modulate the on-chip clock signal to provide a first clock signal to a first circuit and a second clock signal to a second circuit. The first clock signal and the second clock signal are in a multicycle phase relationship.

Abstract: Clock circuits designed to compensate for supply voltage fluctuations (e.g., supply voltage droops) in central processing units (CPUs) are described. The clock circuits described herein involve reducing the clock frequency in response to a decrease to the supply voltage to a value that is approximately equal (or below) to the maximum operating frequency of the CPU at that particular supply voltage. The clock circuits described herein may include a frequency locked loops (FLL). Such FLLs may be designed to lock to a reference frequency when the supply voltage is approximately constant and to deviate from the reference frequency in response to variations in the supply voltage. In some embodiments, an FLL operates in the same supply voltage domain as the CPU.

Abstract: In some examples, machine learning based incident classification and resolution may include analyzing an issue associated with performance of a task or operation of an application or a device, and determining, based on the analysis of the issue and based on a machine learning based automated incident resolution model, whether the issue is appropriate for automated resolution. If so, automated resolution of the issue may be implemented to resolve the issue. Alternatively, a machine learning based incident classification model may be used to determine whether an incident associated with the issue is actionable or non-actionable. If the incident is actionable, a machine learning based incident ticket creation and routing model may be used to generate an incident ticket associated with the incident, and determine support personnel selected from a plurality of support personnel to resolve the incident ticket.