Patents by Inventor Ashish Kushwaha

Ashish Kushwaha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SYSTEM AND METHOD FOR MANUFACTURING AN INTEGRATED CIRCUIT ANTI-FUSE IN CONJUNCTION WITH A TUNGSTEN PLUG PROCESS
    Publication number: 20110221031
    Abstract: A system and method are disclosed for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process. A tungsten plug is formed in a dielectric layer that overlies a portion of P type silicon and an adjacent portion of N type silicon. The dielectric layer is etched to create a first anti-fuse contact opening down to the underlying P type silicon and a second anti-fuse contact opening down to the underlying N type silicon. A metal layer is deposited over the tungsten plug and over the dielectric layer and etched to form an anti-fuse metal contact in each of two anti-fuse contact openings. A bias voltage is applied to the anti-fuse metal contacts to activate the anti-fuse.
    Type: Application
    Filed: March 11, 2011
    Publication date: September 15, 2011
    Applicant: National Semiconductor Corporation
    Inventors: Sergei Drizlikh, Ashish Kushwaha, Thomas James Moutinho, David Tucker
  • System and method for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process
    Patent number: 7915093
    Abstract: A system and method are disclosed for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process. A tungsten plug is formed in a dielectric layer that overlies a portion of P type silicon and an adjacent portion of N type silicon. The dielectric layer is etched to create a first anti-fuse contact opening down to the underlying P type silicon and a second anti-fuse contact opening down to the underlying N type silicon. A metal layer is deposited over the tungsten plug and over the dielectric layer and etched to form an anti-fuse metal contact in each of two anti-fuse contact openings. A bias voltage is applied to the anti-fuse metal contacts to activate the anti-fuse.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: March 29, 2011
    Assignee: National Semiconductor Corporation
    Inventors: Sergei Drizlikh, Ashish Kushwaha, Thomas James Moutinho, David Tucker