Abstract: The present technology includes vertical cell dynamic random-access memory (DRAM) arrays with improved floating body effect. The arrays include one or more bit lines arranged in a first horizontal direction and one or more word lines arranged in a second horizontal direction. The arrays include one or more channels extending in a vertical direction generally orthogonal to the first direction and the second horizontal direction, such that the bit lines intersect with a source/drain region of the plurality of channels, and the word lines intersect with gate regions of the plurality of channels. Arrays include where the source/drain region includes a low bandgap material, where the low bandgap material exhibits a bandgap less than a bandgap of a channel material.

Abstract: Embodiments of the present disclosure relate to a method of forming a contact structure on a substrate. The method includes forming a high aspect ratio (HAR) feature within a substrate having a device formed thereon. The device includes a plurality of channels disposed through a polysilicon layer and extending in a first direction, and an isolation layer disposed on the substrate, the polysilicon layer separated from the isolation layer by a dielectric layer. The forming of the HAR feature is formed a first distance in a second direction from the plurality of channels and includes removing a portion of the isolation layer and the polysilicon layer. The method further includes etching the polysilicon layer to expose a top surface of the isolation layer that is opposite to a surface that is disposed on the surface of the substrate, and exposing a metal layer within the HAR feature.

Abstract: A system and method for fabricating a gate all-around (GAA) field effect transistor (FET) is disclosed. The method includes: forming a plurality of epitaxy layers on a substrate, wherein a formed epitaxy layer includes a plurality of doped channels, a plurality of metal channels, and a dummy gate; depositing a spacer in a source/drain cavity, wherein at least a portion of the spacer is deposited on a dummy gate of a formed epitaxy layer; partially etching the plurality of metal channels of to create a plurality of voids; depositing an inner spacer in each void of the plurality of voids; and depositing a stressed metal filler in the source/drain cavity.

Abstract: A system and method for fabricating a plurality of gate all around (GAA) complementary field effect transistors (CFETs). The fabrication method includes: fabricating a plurality of adjacent epitaxy layers, each of the plurality of epitaxy layers separated by a source/drain (S/D) canyon, each canyon defined by a sidewall of a first GAA CFET, and a sidewall of a second GAA CFET; depositing a dummy fill based on a target depth height into the S/D canyon; depositing a spacer cover on the sidewall of the first GAA CFET, and on the sidewall of the second GAA CFET; etching away the dummy fill to create a void in the S/D canyon; and depositing an isolator in the void at the target depth height.

Abstract: A system and method for forming an isolator in a complementary field effect transistor (CFET) is disclosed. In one aspect the method includes: fabricating a plurality of CFET devices, each device including a first metal-oxide-semiconductor (MOS) device and a second MOS device, wherein the first MOS device and the second MOS device are complementary; removing a filler between the first MOS device and the second MOS device of a first CFET device; depositing a dielectric material between the first CFET device and a second CFET device to fill a void between the first MOS device and the second MOS device of the first CFET device; etching the dielectric material; repeating the depositing and etching steps to fill the void between the first MOS device and the second MOS device of the first CFET device; and performing a final etching to remove the dielectric material between the first and second CFET.

Abstract: Embodiments of the disclosure advantageously provide semiconductor devices, fin field effect transistors (FinFETs) in particular, and methods of manufacturing such devices having improved effective capacitance (Ceff). The FinFETs include a gate structure in which airgaps are provided by recessing a high-k material layer disposed between the gate structure and a spacer layer, thereby reducing the effective dielectric constant in the high-k dielectric layer and improving effective capacitance (Ceff) of the device.

Abstract: A method of forming a portion of a gate-all-around field-effect transistor (GAA FET) includes forming placeholders, each interfacing with an extension region via a cap layer, in recesses formed in portions of a substrate isolated by shallow trench isolations (STIs), the recesses extending into an inter-layer dielectric (ILD) formed on the substrate, removing the placeholders selectively to the substrate, the cap layers, and the STIs, forming selective cap layers at bottoms of the recesses, performing a substrate removal process to isotropically etch the substrate within the recesses, performing a conformal deposition process to form a spacer on exposed surfaces of the substrate and the selective cap layers within the recesses, sculpting the spacer on sidewalls of the substrate and the STIs within the recesses, performing a cap layer removal process to remove the cap layers within the recesses, and forming metal contacts within the recesses.

Abstract: A semiconductor structure forming a complementary field-effect transistor (CFET) includes a metal gate, a bottom field effect transistor (FET) module, the bottom FET module including a plurality of channel layers extending through the metal gate in a first direction, and a bottom source/drain (S/D) contact electrically connected to the plurality of channel layers via a bottom epitaxial (epi) S/D and a bottom interface, and a top FET module stacked on the bottom FET module in a second direction that is orthogonal to the first direction, the top FET module including a plurality of channel layers extending through the metal gate in the first direction, and a top source/drain (S/D) contact electrically connected to the plurality of channel layers via a top epitaxial (epi) S/D and a top interface, wherein the bottom S/D contact and the top S/D contact each comprise cobalt (Co) or tungsten (W).

Abstract: One or more embodiments of the disclosure are directed to methods of forming semiconductor devices, e.g., gate-all-around (GAA) transistors that are used in FEOL and/or BEOL processes. The processes described herein may be integrated and performed in any suitable cluster tool. Some embodiments of the disclosure are directed to cavity shaping processes. Further embodiments of the disclosure are directed to logic transistors with wrap-around backside source/drain contact.

Abstract: The present technology includes semiconductor devices with improved stress in a channel region. The semiconductor devices include a substrate, a source region, a drain region, a channel region that includes at least one channel located between the source and the drain, a first gate region, and a second gate region. The first gate region includes a self-aligned single diffusion break, and the second gate region includes a first gate enclosing the channel between the source region and the drain region. The self-aligned single diffusion break also contains a stressed dielectric material having a stress of about 500 MPa or greater.

Abstract: The present technology includes semiconductor devices with improved stress in a channel region. The semiconductor device includes a substrate, a source region, a drain region, a channel region that includes at least one channel located between the source and the drain. Devices include a first gate region having a first self-aligned single diffusion break in a n-MOS region, and a second gate region includes having a self-aligned single diffusion break in a p-MOS region. The second self-aligned single diffusion break also contains a liner and a compressive stressed material, where the stressed metal fill exhibits a compressive stress of about 350 MPa or greater.

Abstract: The present technology includes semiconductor devices with improved stress in a channel region. The semiconductor device includes a substrate, a source region, a drain region, a channel region that includes at least one channel located between the source and the drain, a first gate region, and a second gate region. The first gate region includes a self-aligned single diffusion break, and the second gate region includes a first gate enclosing the channel between the source region and the drain region. The self-aligned single diffusion break also contains a dielectric liner and a stressed metal fill, where the stressed metal fill exhibits a stress of about 350 MPa or greater.

Abstract: Embodiments of processing a substrate are provided herein. In some embodiments, a method of processing a substrate includes: depositing, via a first epitaxial growth process, an n-doped silicon material onto a substrate to form an n-doped layer while adjusting a ratio of dopant precursor to silicon precursor so that a dopant concentration of the n-doped layer increases from a bottom of the n-doped layer to a top of the n-doped layer; etching the n-doped layer to form a plurality of trenches having sidewalls that are tapered and a plurality of n-doped pillars therebetween; and filling the plurality of trenches with a p-doped material via a second epitaxial growth process to form a plurality of p-doped pillars.

Abstract: A silicon carbide transistor may be formed with a channel that includes a p-doped region between n-doped source and drain regions. A counter-doped region may be formed at the top of the channel directly underneath the gate oxide. Instead of using the conventional doping levels for the p-doped region, the doping concentration may be increase to be greater than about 1e18 cm3. The transistor may also include pocket regions on one or both sides of the channel. The pocket regions may be formed in the counter-doped region and may extend up to the gate oxide. These improvements individually and/or in combination may increase the current in the channel of the transistor without significantly increasing the threshold voltage beyond acceptable operating limits.

Abstract: Disclosed are systems, methods, and apparatus of an automated and self-service kiosk that allows customers to select inventory items available from the kiosk and walk or move away with selected inventory item(s) without having to process payment, identify the inventory item(s), or provide any other form of checkout. After a customer has picked one or more items and departed the kiosk, the picked items are determined and the customer charged for the items. For example, one or more of detected weight changes measured at the kiosk and/or images generated at the kiosk may be used to identify items picked by the customer from the kiosk.

Abstract: Disclosed are systems, methods, and apparatus of an automated and self-service kiosk that allows customers to select inventory items available from the kiosk and walk or move away with selected inventory item(s) without having to process payment, identify the inventory item(s), or provide any other form of checkout. After a customer has picked one or more items and departed the kiosk, the picked items are determined and the customer charged for the items. For example, one or more of detected weight changes measured at the kiosk and/or images generated at the kiosk may be used to identify items picked by the customer from the kiosk.

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a semiconductor material between source regions and drain regions of the device. The method includes formation of a cladding material on a first material followed by a dry oxidation process resulting rearrangement of the cladding material and first material.

Abstract: Examples of the present technology include processing methods to incorporate stress in a channel region of a semiconductor transistor. The methods may include depositing a stressed material on an adjacent layer, where the adjacent layer is disposed between the stressed material and semiconductor material having an incorporated dopant. The adjacent layer may be characterized by an increased stress level after the deposition of the stressed material. The method may further include heating the stressed material and the adjacent layer, and removing the stressed material from the adjacent layer. The adjacent layer retains at least a portion of the increased stress after the removal of the stressed material. Examples of the present technology also include semiconductor structures having a conductive layer with first stress, and an intermediate layer with second stress in contact with the conductive layer. The second tensile stress may be at least ten times the first tensile stress.

Abstract: Processing methods may be performed to form an airgap spacer on a semiconductor substrate. The methods may include forming a spacer structure including a first material and a second material different from the first material. The methods may include forming a source/drain structure. The source/drain structure may be offset from the second material of the spacer structure by at least one other material. The methods may also include etching the second material from the spacer structure to form the airgap. The source/drain structure may be unexposed to etchant materials during the etching.

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming distinct and separate bottom dielectric isolation layers underneath the source/drain and underneath the gate of a gate all around device. Selectively remove of the bottom dielectric isolation layer underneath the source/drain results in better backside power rail (BPR) via alignment to the source/drain epi and reduces reliability and gate-shorting problems.