Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming distinct and separate bottom dielectric isolation layers underneath the source/drain and underneath the gate of a gate all around device. Selectively remove of the bottom dielectric isolation layer underneath the source/drain results in better backside power rail (BPR) via alignment to the source/drain epi and reduces reliability and gate-shorting problems.

Abstract: A silicon carbide transistor may be formed with a channel that includes a p-doped region between n-doped source and drain regions. A counter-doped region may be formed at the top of the channel directly underneath the gate oxide. Instead of using the conventional doping levels for the p-doped region, the doping concentration may be increase to be greater than about 1e18 cm3. The transistor may also include pocket regions on one or both sides of the channel. The pocket regions may be formed in the counter-doped region and may extend up to the gate oxide. These improvements individually and/or in combination may increase the current in the channel of the transistor without significantly increasing the threshold voltage beyond acceptable operating limits.

Abstract: Embodiments of the present disclosure generally relate to metal gate devices. In one or more embodiments, a method for preparing a device with an airgap is provided and includes depositing a silicon-containing layer on inner surfaces of trenches formed in a metal-gate layer disposed on a substrate, depositing a carbon-containing layer on the silicon-containing layer in the trenches, the carbon-containing layer is deposited to fill at least a lower half of the trenches from the bottom, and leaving a temporary gap within each trench at the top. The method also includes depositing a low-k dielectric layer on the carbon-containing layer and the silicon-containing layer to fill the temporary gap, and exposing at least the carbon-containing layer to a treatment process to remove the carbon-containing layer and form the airgap between the silicon-containing layer and the low-k dielectric layer.

Abstract: Semiconductor devices and methods of manufacturing the same are described. Transistors are fabricated using a standard process flow. A via opening extending from the top surface of the substrate to a bottom surface of the wafer device is formed, thus allowing nano TSV for high density packaging, as well as connecting the device to the backside power rail. A metal is deposited in the via opening, and the bottom surface of the wafer device is bound to a bonding wafer. The substrate is optionally thinned, and a contact electrically connected to the metal is formed.

Abstract: Methods and structure for gate-all-around (GAA) semiconductor device that can support multiple threshold voltages. The semiconductor device can include a first channel. The first channel can overlaid by a first dielectric layer. The first dielectric layer can be overlaid by a second dielectric layer. The semiconductor device can include a second channel. The second channel can be overlaid by a third dielectric layer. The first dielectric layer can be a doped dielectric layer. The the third dielectric layer can be overlaid by a fourth dielectric layer. The semiconductor device can include a work-function metal layer overlaying the second dielectric layer and the fourth dielectric layer.

Abstract: The present technology includes methods, devices and systems for forming advanced memory structures, and devices therefrom. Devices include a transistor having one or more bit lines arranged in a first horizontal direction, one or more word lines arranged in a second horizontal direction, and one or more channels extending in a vertical direction that is generally orthogonal to the first horizontal direction and the second horizontal direction. Devices include a capacitor overlying the transistor, where the transistor extends from a first end of a DRAM array to the capacitor, and the capacitor extends from the transistor to a second end of the DRAM array. Devices include a periphery transistor having a contact side and a second side, where the contact side of the periphery transistor is bonded to the first end of the DRAM array and one or more landing pads formed between the transistor and the periphery transistor.

Abstract: The present technology includes semiconductor devices and methods with improved contact resistivity. Semiconductor devices include a substrate base, a silicon oxide disposed on the base defining one or more features, a non-magnetic transition-metal doped contact silicide layer disposed on the substrate in the one or more features, and at least a first metal layer. The non-magnetic transition-metal doped contact silicide layer includes a non-magnetic transition-metal, a first metal, and a silicon containing compound, and includes greater than or about 8.0 E+13 per cm2 non-magnetic transition-metal atoms. The first metal layer includes the first metal and overlies the non-magnetic transition-metal doped contact silicide layer.

Abstract: Described are semiconductor devices, e.g., GAA, FinFET, CFET, having a bilayer dielectric wall. Methods of forming a semiconductor device form a bilayer dielectric wall during the formation of the shallow trench isolation (STI). The first or liner dielectric layer of the bilayer dielectric wall is designed to allow the second or core dielectric layer to withstand downstream etching and to be removed prior to formation of the source/drain epitaxial regions. In some embodiments, the core dielectric layer is removed to form an airgap, mitigating the performance penalty associated with the bilayer dielectric wall.

Abstract: Semiconductor devices and methods of manufacturing the same are described. The method includes forming distinct and separate bottom dielectric isolation layers underneath the source/drain and underneath the gate of a gate all around device. Selectively remove of the bottom dielectric isolation layer underneath the source/drain results in better backside power rail (BPR) via alignment to the source/drain epi and reduces reliability and gate-shorting problems.

Abstract: A method of forming a semiconductor device is provided. The method includes forming an etch stop layer on a substrate having a first thickness, forming an epitaxial layer on the etch stop layer, and forming a wafer device on the epitaxial layer. The wafer device is bonded to a bonding wafer using hybrid bonding. The substrate is then ground to a second thickness less than the first thickness and planarized to a third thickness less than the second thickness. A mask layer is deposited on a bottom surface of the etch stop layer, and at least one via opening is formed in the mask layer. The etch stop layer is selectively removed, and the mask layer is removed to expose the substrate at the third thickness.

Abstract: A method of forming a portion of a gate-all-around field-effect transistor (GAA FET) includes performing an isotropic etch process to partially etch a substrate from source/drain (S/D) recesses extending into a front inter-layer dielectric (ILD) formed on the substrate, performing a substrate nitridation process to form nitride layers on inner surfaces of the S/D recesses, and performing a substrate removal process to selectively etch the substrate while protecting underlying extension regions within the S/D recesses by the nitride layers and form ILD recesses.

Abstract: A method of forming backside contacts to source/drain (S/D) regions of a semiconductor structure includes removing a substrate selectively to shallow trench isolations (STIs) and the extension regions to form first recesses between the STIs, filling the first recesses with first dielectric material, forming second recesses aligned to the S/D regions through the first dielectric material, and forming backside contacts to the extension regions within the second recesses.

Abstract: A method of forming a semiconductor device is provided. The method includes forming a superlattice structure on a substrate and etching source and drain trenches adjacent to the superlattice structure. The source and drain trenches are expanded to form cavities, which are filled with a sacrificial material. A source region and a drain region are formed in the trenches. Contacts to the transistor and gate are formed. Backside processing is then performed by flipping the substrate, depositing an interlayer dielectric on the bottom surface, and etching a backside power rail via that is expanded into a damascene trench. The sacrificial material is removed to create openings extending to the damascene trench, and a metal fill is deposited in the openings and trench.

Abstract: Horizontal gate-all-around devices and methods of manufacturing are described. The hGAA devices include a fully-depleted silicon-on-insulator (FD-SOI) under the channel layers in the same footprint as the hGAA. The buried dielectric isolation layer of the FD-SOI includes one or more of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), and a high-k material, and the buried dielectric isolation layer has a thickness in a range of from 0 nm to 10 nm.

Abstract: A method of forming a portion of a gate-all-around field-effect transistor (GAA FET) includes forming placeholders, each interfacing with an extension region electrically isolated from replacement-metal-gate (RMG) stacks by inner spacers, in recesses formed within portions of a substrate isolated by shallow trench isolations (STIs), the recesses extending into a front inter-layer dielectric (ILD) formed on the substrate, removing the placeholders selectively to the substrate and the STIs, forming a cavity at an exposed surface of the extension region within each of the recesses, forming a contact layer within the cavity, forming an interface on the contact layer, and a contact metallization process to form a metal contact within each of the recesses, selectively etching the substrate against the RMG stacks and form ILD recesses between adjacent metal contacts, forming a dielectric liner surrounding the metal contacts, and forming a back ILD in each of the ILD recesses.

Abstract: Methods and structure for static random-access memory (SRAM) devices with SRAM cells that have backside power delivery networks. A semiconductor device can include one or more static random-access memory cells. Each SRAM cell can include a backside power delivery network with a drain voltage rail and a source voltage rail. Each SRAM cell can also include a memory layer overlaying the backside power delivery network. The memory layer can implement an SRAM memory element. The drain voltage rail and the source voltage rail are connected to contacts at a top of the SRAM memory element. Each SRAM cell can also include a frontside layer overlaying the memory layer. The memory layer can include a word line and a bit line that are connected to the top of the SRAM memory element.

Abstract: Described are methods for forming complementary field-effect transistor (CFET), or other vertically aligned semiconductor structures, utilizing a sequential self-aligning process. In one example, a method of forming a complementary field-effect transistor (CFET) is provide. The method includes replacing top sacrificial layers interleaved between channel layers in a top superlattice of a top device structure with top replacement metal gate layers, the top device structure disposed on a bottom device structure, the bottom device structure disposed on a first substrate layer; securing a second substrate layer to the top device structure and removing the first substrate layer from the bottom device structure; and replacing bottom sacrificial layers interleaved between channel layers in a bottom superlattice of the bottom device structure with bottom replacement metal gate layers.

Abstract: A method for isolating a source-drain of a complementary field-effect-transistor (CFET) stack incorporates a bottom-up fill process to form an isolation layer between vertical structures. The method may include forming an opening to expose a material of a bottom stack of a CFET structure that includes a top stack positioned vertically over the bottom stack where the opening has an aspect ratio of width to depth of approximately 15 or greater. A source-drain isolation (SDI) layer is then formed on the material of the bottom stacks of the CFET structure using a bottom-up fill process that includes depositing an SDI material and etching of the SDI material to achieve formation of the SDI layer. The SDI layer is positioned to electrically isolate source-drains of the bottom stack from source-drains of the top stack.

Abstract: Horizontal gate-all-around devices and methods of manufacturing are described. The hGAA devices include a fully-depleted silicon-on-insulator (FD-SOI) under the channel layers in the same footprint as the hGAA. The buried dielectric insulating layer of the FD-SOI includes one or more of silicon oxide (SiOx), silicon nitride (SiN), silicon carbide (SiC), and a high-k material, and the buried dielectric insulating layer has a thickness in a range of from 0 nm to 10 nm.

Abstract: The present technology includes vertical cell dynamic random-access memory (DRAM) arrays with improved floating body effect. The arrays include one or more bit lines arranged in a first horizontal direction and one or more word lines arranged in a second horizontal direction. The arrays include one or more channels extending in a vertical direction generally orthogonal to the first direction and the second horizontal direction, such that the bit lines intersect with a source/drain region of the plurality of channels, and the word lines intersect with gate regions of the plurality of channels. Arrays include where the source/drain region includes a low bandgap material, where the low bandgap material exhibits a bandgap less than a bandgap of a channel material.