Abstract: The present subject matter discloses a system and method for automatically detecting and quantifying a plaque/stenosis in a vascular ultrasound scan data in real time using Deep learning models. The system receives a video data and selects one or more frames/images for further processing to detect and quantify the plaque in the artery. Based on the selected one or more frames, the system detects a region of interest (ROI) and further processes the ROI. The system selects end points of a deposits of the plaque by taking a maximum length of the plaque in the artery/plaque boundary and determines the orientation of the vascular ultrasound scan. Based on the orientation and the selected end points, the system determines a vessel/artery boundary to identify a size of the plaque. Based on the determined vessel boundary and the orientation, the system determines plaque segments and measures parameters of the plaque.

Abstract: A vehicle-use air conditioning device that supplies air to a side vent aperture portion regardless of a discharge mode, and allows a discharge of air from a defrost aperture portion when a discharge mode that maximizes a ratio of air blown to a passage communicating with a foot aperture portion is employed, is such that a change in an amount of air supplied from the defrost aperture portion is restricted using a simple structure that does not necessitate fine adjustment, even when an air passage on a downstream side of the side vent aperture portion is closed.

Abstract: A power supply detection circuit for an integrated circuit (IC) includes a reference voltage circuit and a comparator circuit. The reference voltage circuit produces a reference voltage from the supply voltage at a reference voltage node. The comparator circuit includes a first p-type metal oxide semiconductor (PMOS) transistor with a source coupled to a positive supply terminal, a gate receiving the reference voltage, and a drain connected to a comparator output terminal. A first n-type metal oxide semiconductor (NMOS) transistor has a drain connected to the comparator output terminal, a source connected to the negative supply terminal, and a gate receiving a second voltage that varies relative to the supply voltage. A second PMOS transistor has a source coupled to the positive supply terminal, a gate connected to the reference voltage node, and a drain providing the second voltage and coupled to a filter.

Abstract: A driver circuit drives a high voltage I/O interface using stacked low voltage devices in the pull-up and pull-down portions of the driver. The transistor closest to the PAD in the pull-up portion receives a dynamically adjusted gate bias voltage adjusted based on the value of the data supplied to the output circuit and the transistor in the pull-down portion closest to the PAD receives the same dynamically adjusted gate bias voltage. The transistors closest to the power supply nodes receive gate voltages that are level shifted from the core voltage levels of the data supplied to the output circuit. The transistors in the middle of the pull-up and pull-down transistor stacks receive respective static gate voltages. The bias voltages are selected such that the gate-drain, source-drain, and gate-source voltages of the transistors in the output circuit do not exceed the voltage tolerance levels of the low voltage devices.

Abstract: A driver circuit drives a high voltage I/O interface using stacked low voltage devices in the pull-up and pull-down portions of the driver. The transistor closest to the PAD in the pull-up portion receives a dynamically adjusted gate bias voltage adjusted based on the value of the data supplied to the output circuit and the transistor in the pull-down portion closest to the PAD receives the same dynamically adjusted gate bias voltage. The transistors closest to the power supply nodes receive gate voltages that are level shifted from the core voltage levels of the data supplied to the output circuit. The transistors in the middle of the pull-up and pull-down transistor stacks receive respective static gate voltages. The bias voltages are selected such that the gate-drain, source-drain, and gate-source voltages of the transistors in the output circuit do not exceed the voltage tolerance levels of the low voltage devices.

Abstract: A receiver circuit holds an output voltage at a first output voltage level using a first device of a first type coupled between a first node and a first power supply node, and a second device of a second type coupled between the first node and the first power supply node. The first device is selectively enabled using an input signal. The second device is selectively enabled using a feedback signal. The second device is substantially larger than the first device. The receiver circuit switches the output voltage from the first output voltage level to a second output voltage level responsive to an input voltage level transitioning across a first threshold voltage level from a first input voltage level to a second input voltage level.

Abstract: The invention relates to a system and method to reduce perchlorate in wastewater utilizing perchlorate-reducing bacteria, sulfur as an electron donor and mollusk shells as alkalinity agent. Embodiments of the invention include a perchlorate-reduction system comprising a bioreactor unit having perchlorate-reducing media comprising elemental sulfur, oyster shells and a microbial community, and can further include an optional pretreatment unit, wastewater-catchment and/or post-treatment components. Embodiments of the method include multiple steps utilizing the system and additional process steps that achieve enhanced perchlorate reduction.

Abstract: The invention relates to a system and method to reduce perchlorate in wastewater utilizing perchlorate-reducing bacteria, sulfur as an electron donor and mollusk shells as alkalinity agent. Embodiments of the invention include a perchlorate-reduction system comprising a bioreactor unit having perchlorate-reducing media comprising elemental sulfur, oyster shells and a microbial community, and can further include an optional pretreatment unit, wastewater-catchment and/or post-treatment components. Embodiments of the method include multiple steps utilizing the system and additional process steps that achieve enhanced perchlorate reduction.