Patents by Inventor Ashish Senapati
Ashish Senapati has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11101812Abstract: Various embodiments relate to analog-to-digital converter (ADC) controllers. An ADC controller may include a number of contexts configured for coupling to an ADC, wherein each context having at least one register for storing at least one configurable parameter. The ADC controller may also include a sequencer operatively coupled to the number of contexts and configured to perform a programmed conversion sequence based on one or more configurable parameters of one or more contexts of the number of contexts. Methods of performing an analog-to-digital (A/D) conversion sequence, and methods of configuring a number of contexts for an analog-to-digital converter (ADC) controller, are also disclosed.Type: GrantFiled: December 31, 2019Date of Patent: August 24, 2021Assignee: Microchip Technology IncorporatedInventors: Ashish Senapati, Kevin Kilzer, Prashanth Pulipaka
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Publication number: 20200136635Abstract: Various embodiments relate to analog-to-digital converter (ADC) controllers. An ADC controller may include a number of contexts configured for coupling to an ADC, wherein each context having at least one register for storing at least one configurable parameter. The ADC controller may also include a sequencer operatively coupled to the number of contexts and configured to perform a programmed conversion sequence based on one or more configurable parameters of one or more contexts of the number of contexts. Methods of performing an analog-to-digital (A/D) conversion sequence, and methods of configuring a number of contexts for an analog-to-digital converter (ADC) controller, are also disclosed.Type: ApplicationFiled: December 31, 2019Publication date: April 30, 2020Inventors: Ashish Senapati, Kevin Kilzer, Prashanth Pulipaka
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Patent number: 10536156Abstract: Various embodiments relate to analog-to-digital converter (ADC) controllers. An ADC controller may include a number of input channels and an ADC selectively coupled to each input channel of the number of input channels. The ADC controller may further include a number of contexts operatively coupled to the ADC, wherein each context of the number of contexts is associated with an input channel of the number of input channels. Further, each context may include at least one register for storing at least one configurable parameter. The ADC controller may also include a sequencer operatively coupled to the number of context and configured to perform a programmed conversion sequence on one or more input channels of the number of input channels based on one or more configurable parameters of one or more contexts of the number of contexts.Type: GrantFiled: October 16, 2018Date of Patent: January 14, 2020Assignee: Microchip Technology IncorporatedInventors: Ashish Senapati, Kevin Kilzer, Prashanth Pulipaka
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Patent number: 10255073Abstract: An 8-bit microprocessor has a program memory having a 16-bit instruction word size and a data memory having an 8-bit data size. An instruction word has a payload size for an address of up to 12 bits. The microprocessor furthermore has a central processing unit coupled with the program memory and the data memory, a bank select register configured to select one of up to 64 memory banks, and an indirect addressing register operable to address up to 16KB of data memory. The CPU is configured to execute a first move instruction having two instruction words and being configured to only access the lower 4KB of the data memory and a second move instruction having three instruction words and configured to access the entire data memory.Type: GrantFiled: May 11, 2017Date of Patent: April 9, 2019Assignee: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Ashish Senapati, Sean Steedman, Brent Loertscher
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Patent number: 10114776Abstract: A programmable system arbiter for granting access to a system bus among a plurality of arbiter clients and a central processing unit is disclosed. The programmable system arbiter may include one or more interrupt priority registers, each of the one or more interrupt priority registers associated with an interrupt type; and system arbitration logic operable to arbitrate access to the system bus among the plurality of arbiter clients and the CPU based at least on an analysis of a programmed priority order, the programmed priority order comprising a priority order for each of the plurality of arbiter clients, each of a plurality of operating modes of the central processing unit, and each of the one or more interrupt types.Type: GrantFiled: April 27, 2017Date of Patent: October 30, 2018Assignee: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Sean Steedman, Kevin Kilzer, Ashish Senapati, Justin Milks, Prashanth Pulipaka
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Patent number: 10067892Abstract: A microcontroller has a CPU with at least one interrupt input coupled with an interrupt controller, a plurality of peripherals, and a mode register comprising at least one bit controlling an operating mode of the microcontroller. The microcontroller is configured to operate in a first operating mode wherein upon assertion of an interrupt by a peripheral of the microcontroller, the interrupt controller forwards an interrupt signal to the CPU and the peripheral sets an associated interrupt flag, wherein the interrupt causes the CPU to branch to a predefined interrupt address associated with the interrupt input. In a second operating mode, upon assertion of an interrupt by a peripheral of the microcontroller, the interrupt controller forwards an interrupt signal to the CPU and the CPU receives additional interrupt information from the peripheral that generated the interrupt, wherein the additional interrupt information is used to generate a vector address.Type: GrantFiled: March 3, 2016Date of Patent: September 4, 2018Assignee: MICROCHIP TECHNOLOGY INCORPORATEDInventors: Keith Curtis, Ashish Senapati, Anthony Garcia, Vijay Sarvepalli, Prashanth Pulipaka, Kevin Kilzer, David Forst, Rob Kennedy, Primo Castro, Aaron Barton
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Publication number: 20180121380Abstract: A programmable system arbiter for granting access to a system bus among a plurality of arbiter clients and a central processing unit is disclosed. The programmable system arbiter may include one or more interrupt priority registers, each of the one or more interrupt priority registers associated with an interrupt type; and system arbitration logic operable to arbitrate access to the system bus among the plurality of arbiter clients and the CPU based at least on an analysis of a programmed priority order, the programmed priority order comprising a priority order for each of the plurality of arbiter clients, each of a plurality of operating modes of the central processing unit, and each of the one or more interrupt types.Type: ApplicationFiled: April 27, 2017Publication date: May 3, 2018Applicant: Microchip Technology IncorporatedInventors: Sean Steedman, Kevin Kilzer, Ashish Senapati, Justin Milks, Prashanth Pulipaka
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Publication number: 20170329611Abstract: An 8-bit microprocessor has a program memory having a 16-bit instruction word size and a data memory having an 8-bit data size. An instruction word has a payload size for an address of up to 12 bits. The microprocessor furthermore has a central processing unit coupled with the program memory and the data memory, a bank select register configured to select one of up to 64 memory banks, and an indirect addressing register operable to address up to 16 KB of data memory. The CPU is configured to execute a first move instruction having two instruction words and being configured to only access the lower 4 KB of the data memory and a second move instruction having three instruction words and configured to access the entire data memory.Type: ApplicationFiled: May 11, 2017Publication date: November 16, 2017Applicant: Microchip Technology IncorporatedInventors: Ashish Senapati, Sean Steedman, Brent Loertscher
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Publication number: 20160259741Abstract: A microcontroller has a CPU with at least one interrupt input coupled with an interrupt controller, a plurality of peripherals, and a mode register comprising at least one bit controlling an operating mode of the microcontroller. The microcontroller is configured to operate in a first operating mode wherein upon assertion of an interrupt by a peripheral of the microcontroller, the interrupt controller forwards an interrupt signal to the CPU and the peripheral sets an associated interrupt flag, wherein the interrupt causes the CPU to branch to a predefined interrupt address associated with the interrupt input. In a second operating mode, upon assertion of an interrupt by a peripheral of the microcontroller, the interrupt controller forwards an interrupt signal to the CPU and the CPU receives additional interrupt information from the peripheral that generated the interrupt, wherein the additional interrupt information is used to generate a vector address.Type: ApplicationFiled: March 3, 2016Publication date: September 8, 2016Applicant: Microchip Technology IncorporatedInventors: Keith Curtis, Ashish Senapati, Anthony Garcia, Vijay Sarvepalli, Prashanth Pulipaka, Kevin Kilzer, David Forst, Rob Kennedy, Primo Castro, Aaron Barton