Patents by Inventor Ashish Sharma KUMAR

Ashish Sharma KUMAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CONTINUOUS TIME DELTA-SIGMA MODULATOR WITH A TIME INTERLEAVED QUANTIZATION FUNCTION
    Publication number: 20170288693
    Abstract: A wide band continuous time delta-sigma modulator implements a time interleaved quantization processing operation. The modulator may provide for an inherent finite impulse response filtering in the feedback loop. Additionally, further finite impulse response filtering in each time interleaved feedback path may be provided.
    Type: Application
    Filed: March 21, 2017
    Publication date: October 5, 2017
    Applicant: STMicroelectronics International N.V.
    Inventors: Ashish Sharma Kumar, Rajeev Jain, Chandrajit Debnath
  • Adaptive delay based asynchronous successive approximation analog-to-digital converter
    Patent number: 9300317
    Abstract: An asynchronous SAR ADC converts an analog signal into a series of digital pulses in an efficient, low power manner. In synchronous SAR ADC circuits, a separate and cumbersome clock signal is used to trigger the internal circuitry of the SAR ADC. Instead of triggering the components of the SAR DAC synchronously with a clock signal, the asynchronous solution uses its own internal signals to trigger its components in an asynchronous cyclic manner. Further, in order to increase efficiency and guard against circuit failures due to difficulties arising from transient signals, the asynchronous SAR ADC may also include a delay circuit for introducing a variable delay to the SAR ADC cycle.
    Type: Grant
    Filed: November 3, 2015
    Date of Patent: March 29, 2016
    Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Rakesh Malik, Chandrajit Debnath, Ashish Sharma Kumar, Pratap Narayan Singh
  • ADAPTIVE DELAY BASED ASYNCHRONOUS SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER
    Publication number: 20160056830
    Abstract: An asynchronous SAR ADC converts an analog signal into a series of digital pulses in an efficient, low power manner. In synchronous SAR ADC circuits, a separate and cumbersome clock signal is used to trigger the internal circuitry of the SAR ADC. Instead of triggering the components of the SAR DAC synchronously with a clock signal, the asynchronous solution uses its own internal signals to trigger its components in an asynchronous cyclic manner. Further, in order to increase efficiency and guard against circuit failures due to difficulties arising from transient signals, the asynchronous SAR ADC may also include a delay circuit for introducing a variable delay to the SAR ADC cycle.
    Type: Application
    Filed: November 3, 2015
    Publication date: February 25, 2016
    Applicant: STMICROELECTRONICS INTERNATIONAL N.V.
    Inventors: Rakesh Malik, Chandrajit Debnath, Ashish Sharma Kumar, Pratap Narayan Singh
  • Adaptive delay based asynchronous successive approximation analog-to-digital converter
    Patent number: 9258008
    Abstract: An asynchronous SAR ADC to convert an analog signal into a series of digital pulses in an efficient, low power manner. In synchronous SAR ADC circuits, a separate and cumbersome clock signal is used to trigger the internal circuitry of the SAR ADC. Instead of triggering the components of the SAR DAC synchronously with a clock signal, the asynchronous solution uses its own internal signals to trigger its components in an asynchronous cyclic manner. Further, in order to increase efficiency and guard against circuit failures due to difficulties arising from transient signals, the asynchronous SAR ADC may also include a delay circuit for introducing a variable delay to the SAR ADC cycle.
    Type: Grant
    Filed: March 31, 2014
    Date of Patent: February 9, 2016
    Assignee: STMicroelectronics International N.V.
    Inventors: Pratap Narayan Singh, Ashish Sharma Kumar, Chandrajit Debnath, Rakesh Malik
  • ADAPTIVE DELAY BASED ASYNCHRONOUS SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERTER
    Publication number: 20150280728
    Abstract: An asynchronous SAR ADC to convert an analog signal into a series of digital pulses in an efficient, low power manner. In synchronous SAR ADC circuits, a separate and cumbersome clock signal is used to trigger the internal circuitry of the SAR ADC. Instead of triggering the components of the SAR DAC synchronously with a clock signal, the asynchronous solution uses its own internal signals to trigger its components in an asynchronous cyclic manner. Further, in order to increase efficiency and guard against circuit failures due to difficulties arising from transient signals, the asynchronous SAR ADC may also include a delay circuit for introducing a variable delay to the SAR ADC cycle.
    Type: Application
    Filed: March 31, 2014
    Publication date: October 1, 2015
    Applicant: STMicroelectronics International N.V.
    Inventors: Pratap Narayan SINGH, Ashish Sharma KUMAR, Chandrajit DEBNATH, Rakesh MALIK