Abstract: The disclosed technology provides solutions for applying a flare detection model to an image for detecting road flares in an environment by an autonomous vehicle (AV). A method comprises accessing a flare detection model that is trained to recognize a bounded outer region and a bounded inner region; and detect a flare object within the bounded inner region and refrain from detecting an object in the bounded outer region; applying the flare detection model to an image of the environment to recognize an outer region corresponding to a glow of a flare and an inner region that corresponds to the flare in the environment; and detecting the flare in the environment within the inner region based on the inner region being recognized by the flare detection model and contained within the outer region that is also recognized by the flare detection model. Systems and machine-readable media are also provided.

Abstract: Disclosed are embodiments for facilitating approximately-paired simulation-to-real image translation. In some aspects, a method includes receiving, by a processing device performing training on a model, an approximately-paired image pair comprising a real image and a simulated image, wherein the simulated image is generated from the real image using contextual data of the real image; determining, by the processing device using a style encoder of the model, a style difference between a first style vector of the simulated image and a second style vector of the real image, wherein the first style vector and the second style vector encode style features of the simulated image and the real image using a style encoder; and inputting the style difference and the simulated image to a generative adversarial network (GAN) of the model to train the GAN to generate a post-processed simulated image.

Abstract: The invention relates to a process for producing olefins from a feed stream containing hydrocarbons by pyrolytic cracking of the hydrocarbons in a cracker furnace, said process comprising: pre-heating the feed stream outside the cracker furnace; feeding the pre-heated feed stream to a tube in the convection section of the cracker furnace; further pre-heating the feed stream in the convection section; feeding the further pre-heated feed stream to a tube in the radiant section of the cracker furnace; pre-heating an oxygen containing stream; contacting the pre-heated oxygen containing stream with a fuel gas in a burner in the radiant section; and pyrolytic cracking the feed stream in the radiant section resulting in an effluent containing olefins.

Abstract: Systems and techniques are described for Light Detection and Ranging (LiDAR) noise modeling using machine learning (ML). An example method can include collecting, using one or more sensors, a first set of data for a simulation environment and generating, using the first set of data, a point cloud that represents and/or describes the simulation environment. The method can further include collecting, using the one or more sensors, a second set of data for a real-world environment and generating a noise model using the second set of data and a neural network. The method can also include generating, using the noise model and the point cloud, a noisy point cloud that represents and/or describes the real-world environment.

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

Abstract: An information handling system may include a chassis configured to house a plurality of information handling resources, one or more air movers internal to the chassis and arranged to drive airflow proximate to the plurality of information handling systems, and an air-to-liquid radiator internal to the chassis and arranged such that the airflow flows proximate to the air-to-liquid radiator to cool airflow internal to the chassis prior to flowing proximate to at least one of the information handling resources.

Abstract: An information handling system includes a memory device and a processor. The memory device includes first data representing a thermal profile of a motherboard, and second data representing a circuit trace of the motherboard. The circuit trace provides a high-speed data interconnection between two or more circuit devices. The processor determines an average temperature of the circuit trace on the motherboard based upon the first data and the second data, and models a trace layout for the circuit trace on the motherboard based upon the average temperature.

Abstract: A method includes obtaining a time-series of training samples that include one or more states, a ground truth value, an output value produced in the presence of the one or more states, and an actual error value that is defined as a difference between the ground truth value and the output value. The method also includes training a machine learning model using the time-series of training samples such that the machine learning model is configured to determine a condition-dependent error distribution for a current time step based on simulated states for the current time step.

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

Abstract: A generative network may be learned in an adversarial setting with a goal of modifying synthetic data such that a discriminative network may not be able to reliably tell the difference between refined synthetic data and real data. The generative network and discriminative network may work together to learn how to produce more realistic synthetic data with reduced computational cost. The generative network may iteratively learn a function that synthetic data with a goal of generating refined synthetic data that is more difficult for the discriminative network to differentiate from real data, while the discriminative network may be configured to iteratively learn a function that classifies data as either synthetic or real. Over multiple iterations, the generative network may learn to refine the synthetic data to produce refined synthetic data on which other machine learning models may be trained.

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

Abstract: A generative network may be learned in an adversarial setting with a goal of modifying synthetic data such that a discriminative network may not be able to reliably tell the difference between refined synthetic data and real data. The generative network and discriminative network may work together to learn how to produce more realistic synthetic data with reduced computational cost. The generative network may iteratively learn a function that synthetic data with a goal of generating refined synthetic data that is more difficult for the discriminative network to differentiate from real data, while the discriminative network may be configured to iteratively learn a function that classifies data as either synthetic or real. Over multiple iterations, the generative network may learn to refine the synthetic data to produce refined synthetic data on which other machine learning models may be trained.

Abstract: A neural network is trained to defend against adversarial attacks, such as by preparing an input image for classification by a neural network where the input image includes a noise-based perturbation. The input image is divided into source patches. Replacement patches are selected for the source patches by searching a patch library for candidate patches available for replacing ones of those source patches, such as based on sizes of those source patches. A denoised image reconstructed from a number of replacement patches is then output to the neural network for classification. The denoised image may be produced based on reconstruction errors determined for individual candidate patches identified from the patch library. Alternatively, the denoised image may be selected from amongst a number of candidate denoised images. A set of training images is used to construct the patch library, such as based on salient data within patches of those training images.

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

Abstract: A system and method for training a computer-implemented object classifier includes detecting a foreground visual object within a sub-region of a scene, determining a background model of the sub-region of the scene, the background model representing the sub-region when any foreground visual object is absent from that sub-region, and training the object classifier by computer-implemented machine learning using the background model of the sub-region as a negative training example.

Abstract: A Very Long Instruction Word (VLIW) digital signal processor particularly adapted for single instruction multiple data (SIMD) operation on various operand widths and data sizes. A vector compare instruction compares first and second operands and stores compare bits. A companion vector conditional instruction performs conditional operations based upon the state of a corresponding predicate data register bit. A predicate unit performs data processing operations on data in at least one predicate data register including unary operations and binary operations. The predicate unit may also transfer data between a general data register file and the predicate data register file.

Abstract: Systems and techniques for advance cache allocation are described. A described technique includes selecting a job from a plurality of jobs; selecting a processor core from a plurality of processor cores to execute the selected job; receiving a message which describes future memory accesses that will be generated by the selected job; generating a memory burst request based on the message; performing the memory burst request to load data from a memory to at least a dedicated portion of a cache, the cache corresponding to the selected processor core; and starting the selected job on the selected processor core. The technique can include performing an action indicated by a send message to write one or more values from another dedicated portion of the cache to the memory.

Abstract: A system and method for training a computer-implemented object classifier includes detecting a foreground visual object within a sub-region of a scene, determining a background model of the sub-region of the scene, the background model representing the sub-region when any foreground visual object is absent from that sub-region, and training the object classifier by computer-implemented machine learning using the background model of the sub-region as a negative training example.

Abstract: A method generates a high-resolution (HR) image from a low-resolution (LR) image using regression functions. During a training stage, training HR images are downsampled to LR images. A signature is determined for each LR-HR patch pair based on a local ternary pattern (LTP). The signature is a low dimensional descriptor used as an abstraction of the patch pair features. Then, patch pairs with the same signature are clustered, and a regression function which maps the LR patches to the HR patches is determined. In some cases patch pairs of similar signatures can be combined for learning and a single regression function determined, thus decreasing the number of required regression functions. During actual upscaling, LR patches of an input image are similarly processed to obtain the signatures and from the regression functions. The LR patches can then be upscaled using the training regression functions.