Patents by Inventor Ashish VANJARI

Ashish VANJARI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12519383
    Abstract: A circuit includes a microcontroller having a first terminal and a second terminal. The microcontroller is configured to: receive a signal associated with operation of a power converter at the first terminal; adjust a switch control signal at the second terminal responsive to the signal; measure a frequency of the switch control signal; compare the measured frequency responsive to at least one envelope of a set of envelopes to obtain monitoring results; and perform control operations responsive to the monitoring results.
    Type: Grant
    Filed: August 31, 2023
    Date of Patent: January 6, 2026
    Assignee: Texas Instruments Incorporated
    Inventors: Shailesh Ghotgalkar, Mihir Narendra Mody, Ashish Vanjari, Aravindhan Karuppiah, Mohd Farooqui, Biju Mg, Daniel Wu
  • Publication number: 20250291751
    Abstract: In described examples, an integrated circuit includes a first pin, a second pin, a processor, a bus monitor, a clock circuit, and a transceiver. The processor provides to the transceiver and the bus monitor an instruction that indicates an instructed target address, a read/write flag, and a memory address. The transceiver provides to the first pin and the bus monitor a clock signal, and provides to the second pin and the bus monitor a message so that the message includes a messaged target address, the read/write flag, and the memory address. The bus monitor compares the instructed target address to the messaged target address, and provides a signal to the processor in response to the comparison.
    Type: Application
    Filed: May 29, 2025
    Publication date: September 18, 2025
    Inventors: Ashish Vanjari, Mohammed Arif, Shailesh Ganapat Ghotgalkar
  • Patent number: 12321293
    Abstract: In described examples, an integrated circuit includes a first pin, a second pin, a processor, a bus monitor, a clock circuit, and a transceiver. The processor provides to the transceiver and the bus monitor an instruction that indicates an instructed target address, a read/write flag, and a memory address. The transceiver provides to the first pin and the bus monitor a clock signal, and provides to the second pin and the bus monitor a message so that the message includes a messaged target address, the read/write flag, and the memory address. The bus monitor compares the instructed target address to the messaged target address, and provides a signal to the processor in response to the comparison.
    Type: Grant
    Filed: November 17, 2023
    Date of Patent: June 3, 2025
    Assignee: Texas Instruments Incorporated
    Inventors: Ashish Vanjari, Mohammed Arif, Shailesh Ganapat Ghotgalkar
  • Publication number: 20250165416
    Abstract: In described examples, an integrated circuit includes a first pin, a second pin, a processor, a bus monitor, a clock circuit, and a transceiver. The processor provides to the transceiver and the bus monitor an instruction that indicates an instructed target address, a read/write flag, and a memory address. The transceiver provides to the first pin and the bus monitor a clock signal, and provides to the second pin and the bus monitor a message so that the message includes a messaged target address, the read/write flag, and the memory address. The bus monitor compares the instructed target address to the messaged target address, and provides a signal to the processor in response to the comparison.
    Type: Application
    Filed: November 17, 2023
    Publication date: May 22, 2025
    Inventors: Ashish Vanjari, Mohammed Arif, Shailesh Ganapat Ghotgalkar
  • Publication number: 20250079967
    Abstract: A circuit includes a microcontroller having a first terminal and a second terminal. The microcontroller is configured to: receive a signal associated with operation of a power converter at the first terminal; adjust a switch control signal at the second terminal responsive to the signal; measure a frequency of the switch control signal; compare the measured frequency responsive to at least one envelope of a set of envelopes to obtain monitoring results; and perform control operations responsive to the monitoring results.
    Type: Application
    Filed: August 31, 2023
    Publication date: March 6, 2025
    Inventors: Shailesh GHOTGALKAR, Mihir Narendra MODY, Ashish VANJARI, Aravindhan KARUPPIAH, Mohd FAROOQUI, Biju MG, Daniel WU