Patents by Inventor Ashish .

Ashish . has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240411972
    Abstract: A formal verification tool used with a hardware monitor to verify that a hardware design for an electronic device does not comprise a bug or error that can cause an instantiation of the hardware design to fetch an instruction from an out-of-bounds address. Formal assertations for a hardware design are received, wherein the formal assertions assert a formal property that compares a memory address from which an instruction was fetched by an instantiation of the hardware design to an allowable memory address range or an unallowable memory address range associated with an operating state of the instantiation of the hardware design when the fetch was performed. The tool formally verifies that the formal assertations are true for the hardware design to identify whether the hardware design has a bug or error that causes an out-of-bounds violation.
    Type: Application
    Filed: August 16, 2024
    Publication date: December 12, 2024
    Inventors: Ashish Darbari, Iain Singleton
  • Patent number: 12162620
    Abstract: Hybrid-electric aircraft and a series hybrid powertrain configured to power the aircraft for a medium-haul flight. The series hybrid power train includes a plurality of energy storage units, at least one range extending generator, and a plurality of electric propulsors, each coupled to a distribution bus. The electric propulsors can produce a maximum thrust of at least 15 MW. During a cruise regime, the hybrid-electric aircraft can have an airspeed of at least 0.7 Mach at an altitude of less than 32000 feet, and the plurality of electric propulsors can have a fan pressure ratio of between 1.15 and 1.19. The hybrid-electric aircraft can have a degree of hybridization of at least 25% for the medium-haul flight and carbon dioxide equivalent (CO2e) well-to-wake greenhouse gas (GHG) emissions less than 0.25 lbs/Available Seat Mile (ASM).
    Type: Grant
    Filed: October 10, 2022
    Date of Patent: December 10, 2024
    Assignee: Zunum Aero, Inc.
    Inventors: Ashish Andrew Kumar, Burton Matthew Knapp
  • Patent number: 12164462
    Abstract: Systems and methods described herein may relate to data transactions involving a microsector architecture. Control circuitry may organize transactions to and from the microsector architecture to, for example, enable direct addressing transactions as well as batch transactions across multiple microsectors. A data path disposed between programmable logic circuitry of a column of microsectors and a column of row controllers may form a micro-network-on-chip used by a network-on-chip to interface with the programmable logic circuitry.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: December 10, 2024
    Assignee: ALTERA CORPORATION
    Inventors: Ilya K. Ganusov, Ashish Gupta, Chee Hak Teh, Sean R. Atsatt, Scott Jeremy Weber, Parivallal Kannan, Aman Gupta, Gary Brian Wallichs
  • Patent number: 12166122
    Abstract: A memory device structure includes a transistor structure including a gate electrode over a top surface of a fin and adjacent to a sidewall of the fin, a source structure coupled to a first region of the fin and a drain structure coupled to a second region of the fin, where the gate electrode is between the first and the second region. A gate dielectric layer is between the fin and the gate electrode. The memory device structure further includes a capacitor coupled with the transistor structure, the capacitor includes the gate electrode, a ferroelectric layer on a substantially planar uppermost surface of the gate electrode and a word line on the ferroelectric layer.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: December 10, 2024
    Assignee: Intel Corporation
    Inventors: Shriram Shivaraman, Uygar Avci, Ashish Verma Penumatcha, Nazila Haratipour, Seung Hoon Sung, Sou-Chi Chang
  • Patent number: 12164365
    Abstract: An apparatus and method for efficiently managing power consumption among multiple, replicated functional blocks of an integrated circuit. An integrated circuit includes multiple, replicated functional blocks that use separate power domains. Data of a given type is stored in an interleaved manner among at least two of the multiple functional blocks. In one implementation, a prior static allocation determines that only a subset of the functional blocks store the data of the given type. In another implementation, each of the functional blocks stores the data of the given type, and when an idle state has occurred, data of the given type is moved between the multiple functional blocks until one or more functional blocks no longer store data of the given type. When a transition to the idle state has occurred, the functional blocks that do not store the data of the given type are transitioned to a sleep state.
    Type: Grant
    Filed: December 27, 2022
    Date of Patent: December 10, 2024
    Assignees: Advanced Micro Devices, Inc, ATI Technologies ULC
    Inventors: Gia Tung Phan, Ashish Jain, Shang Yang
  • Patent number: 12163728
    Abstract: An appliance cabinet includes a structural envelope having an exterior surface and an interior surface that defines an insulating cavity, wherein the insulating cavity defines an at least partial vacuum. A plurality of silica-based agglomerates are disposed within the insulating cavity, wherein each agglomerate of the plurality of silica-based agglomerates includes silica-based powder insulation material that is water-densified and is at least substantially free of a material binder. A secondary insulation material is disposed within interstitial spaces defined between the plurality of silica-based agglomerates, wherein the plurality of silica-based agglomerates defines an interior structure that resists inward compressive forces exerted as a result of the at least partial vacuum defined within the insulating cavity.
    Type: Grant
    Filed: June 28, 2023
    Date of Patent: December 10, 2024
    Assignee: Whirlpool Corporation
    Inventors: Ashish Nigam, Shayta Roy
  • Patent number: 12164353
    Abstract: A system and method for determining power-performance state transition thresholds in a computing system. A processor comprises several functional blocks and a power manager. Each of the functional blocks produces data corresponding to an activity level associated with the respective functional block. The power manager determines activity levels of the functional blocks and compares the activity level of a given functional block to a threshold to determine if a power-performance state (P-state) transition is indicated. The threshold is determined in part on a current P-state of the given functional block. When the current P-state of the given functional block is relatively high, the threshold activity level to transition to a higher P-state is higher than it would be if the current P-state were relatively low. The power manager is further configured to determine the thresholds based in part on one or more of a type of circuit being monitored and a type of workload being executed.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: December 10, 2024
    Assignees: Advanced Micro Devices, Inc., ATI Technologies ULC
    Inventors: Ashish Jain, Shang Yang
  • Patent number: 12164278
    Abstract: Techniques described herein relate to methods and systems for thermal management of a thermal environment. The method may include using thermal data items from computing devices and time series analysis to predict future thermal values for the thermal data items; performing a clustering analysis using the predicted future thermal values to assign cluster labels to the computing devices; using the cluster labels and the predicted future thermal values to assign predicted thermal status labels to the computing devices; assigning a confidence value to the predicted thermal status labels and ranking the computing devices based on the confidence values; performing an analysis to determine a thermal data item contributing to the assigned thermal status; and sending the results to a thermal environment administrator.
    Type: Grant
    Filed: November 9, 2020
    Date of Patent: December 10, 2024
    Assignee: EMC IP HOLDING COMPANY LLC
    Inventors: Rahul Deo Vishwakarma, Hemant Gaikwad, Ashish Singh
  • Patent number: 12164401
    Abstract: A memory built in self test (MBIST) controller of an MBIST circuit outputs first data. One or more errors is injected in the first data to produce second data. The second data is stored in the memory block. The memory block outputs the second data stored in the memory block. The MBIST controller receives the second data and detects an error in the second data based on a comparison with the first data, the error indicative of a failure of the MBIST. The MBIST controller provides an indication of failure of the MBIST to a processing core external to the MBIST circuit which performs diagnostic action in response to receiving the indication of failure of the MBIST. The processing core validates implementation of the diagnostic action.
    Type: Grant
    Filed: May 17, 2023
    Date of Patent: December 10, 2024
    Assignee: NXP B.V.
    Inventors: Umesh Pratap Singh, Ajay Sharma, Ruchi Bora, Ashish Goel
  • Patent number: 12165218
    Abstract: A provider institution computing system determining a goal of the customer of the provider institution, determining context information related to the goal, generating a first set of sub-goals for the goal of the customer, the first set of sub-goals defining a first group of steps required to be met by the customer to reach the goal, determining a current status of the customer relating to the first set of sub-goals and the goal, generating a second set of sub-goals for the goal of the customer corresponding to a first change in the context information, the second set of sub-goals being different than the first set of sub-goals, wherein the goal remains unchanged upon generating the second set of sub-goals, and responsive to determining that at least one transaction fails to conform with the goal, blocking, by the artificial intelligence circuit, the at least one transaction.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: December 10, 2024
    Assignee: Wells Fargo Bank, N.A.
    Inventors: Nick Gambale, Ashish B Kurani, Kayla Palm, Dana Roytenberg, Eric Vanderleek
  • Patent number: 12163143
    Abstract: The invention generally relates to plant cells and plants modified to increase resistance to necrotrophs or drought and methods of selecting and using the same. More specifically, the invention relates in part to plant cells and/or plants modified to eliminate or reduce as compared to control plants cell the NADPH oxidase activity or expression of certain respiratory burst oxidase homolog (RBOH) proteins and methods of selecting for and using the same.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: December 10, 2024
    Assignee: WISCONSIN ALUMNI RESEARCH FOUNDATION
    Inventors: Ashish Ranjan, Mehdi Kabbage, Damon Lee Smith
  • Publication number: 20240404869
    Abstract: A layered assembly for use in a controlled atmosphere chamber includes a plurality of substrates and an electrically functioning layer embedded between two adjacent substrates of the plurality of substrates, the electrically functioning layer being a material configured to secure the two adjacent substrates together using a solid-state bonding process. An electrical termination area is integral with the electrically functioning layer, and a peripheral sealing band is embedded between and extends around a periphery of internal faces of the two adjacent substrates, the peripheral sealing band being a material configured to secure and seal the two adjacent substrates together using the solid-state bonding process. Dielectric regions are present between the two adjacent substrates and between edge boundaries of the electrically functioning layer, the dielectric regions being sealed between the two adjacent substrates by the peripheral sealing band.
    Type: Application
    Filed: August 14, 2024
    Publication date: December 5, 2024
    Applicant: WATLOW ELECTRIC MANUFACTURING COMPANY
    Inventors: Jason STEPHENS, Guleid HUSSEN, Michael PARKER, Dennis REX, Ashish BHATNAGAR, Brent ELLIOT, Kevin PTASIENSKI
  • Publication number: 20240404122
    Abstract: The present disclosure relates to systems, methods, and non-transitory computer readable media that align objects of a digital image across different perspectives portrayed therein. For instance, in one or more embodiments, the disclosed systems detect one or more user interactions for moving a first object within a first perspective of a digital image. Additionally, the disclosed systems determine a modified alignment of the first object within the first perspective by mapping an alignment of a second object portrayed within a second perspective of the digital image to the first perspective. The disclosed systems further modify the digital image by positioning the first object within the first perspective in accordance with the modified alignment.
    Type: Application
    Filed: June 2, 2023
    Publication date: December 5, 2024
    Inventors: Ashish Jain, Arushi Jain
  • Publication number: 20240403542
    Abstract: The present disclosure relates to systems, methods, and non-transitory computer readable media for performing object-specific undo and/or redo operations. For example, in one or more embodiments, the disclosed systems receive a modified digital design image comprising a first modified object and a second modified object. In some examples, the second modified object is modified after the first modified object. The disclosed systems can generate and utilize an object-specific version representation to undo an edit to the first modified object without undoing edits to the second modified object. The disclosed systems can generate and provide, for display via a user interface, an updated digital design document comprising a reverted first object and the second modified object.
    Type: Application
    Filed: June 2, 2023
    Publication date: December 5, 2024
    Inventors: Ashish Jindal, Praveen Kumar Dhanuka, Vineet Batra
  • Publication number: 20240406229
    Abstract: Aspects of the technology described herein provide a collaborative browsing experience in which real-time browsing activity and saved browsing activity of session collaborators in a collaborative browsing session are shared with the collaborators. A collaborative session may be initiated, which may create a tab group associated with the session and linked to a collaborator. Other collaborators may be invited to join the session, and additional tab groups for each collaborator may be created. The tab groups of the collaborators may be included in a collective tab group, which may be updated in real-time with changes made by any of the collaborators. For example, client changes may be handled locally and communicated to a service to which each client is connected. The service may sequence and broadcast the ordered changes to the clients, which may each implement the changes according to the sequence to synchronize a shared state amongst clients.
    Type: Application
    Filed: August 9, 2024
    Publication date: December 5, 2024
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Avi Ashish VAID, Joseph Jiwoong OAK, Mohamed MANSOUR
  • Publication number: 20240406099
    Abstract: Policy-based network transmission routing is provided by accessing routing metadata in a wrapper of the transmission packet, the routing metadata representing a feature of the source or the destination, comparing the routing metadata to routing policy data associated with each of multiple routing policies defined within a routing policy structure, identifying, based on the comparing, one or more routing policies applicable to the transmission packet, identifying, based on the routing policy data, a highest priority routing policy from the one or more routing policies, the highest priority routing policy defining a route constraint usable to limit a selection of available routes to the destination, and selecting the route from the available routes based on the route constraint.
    Type: Application
    Filed: May 31, 2023
    Publication date: December 5, 2024
    Inventors: Poornananda Gaddehosur RAMACHANDRA, Ashish BHARGAVA, Sumeet MITTAL, Sourav DAS, Randy MILLER, Brian David SWANDER
  • Publication number: 20240403861
    Abstract: A computer system selects a default payment account based on at least one of (a) account balance information for a plurality of accounts of a user or (b) user preferences received from the user. The computer system receives a request for a transaction to transfer funds to a recipient and determines that the transaction causes the account balance of the default payment account to decrease below a user-defined threshold minimum value. The computer system generates a screen display including a link associated with a second account and provides the screen display to a mobile device of the user. The computer system receives a selection of the link associated with the second account, generates an optical code associated with the second account that incorporates a tokenized account number of the second account, and transmits the optical code to the mobile device for the transaction.
    Type: Application
    Filed: August 13, 2024
    Publication date: December 5, 2024
    Applicant: Wells Fargo Bank, N.A.
    Inventor: Ashish Bhoopen Kurani
  • Publication number: 20240406060
    Abstract: An apparatus includes a processor and a memory having instructions stored thereon that, when executed by the processor, cause the apparatus to process a first notification received from a first network node to determine a first status of the first network node. The apparatus is also caused to process a second notification received from a second network node to determine a second status of the second network node. The apparatus is further caused to, response to determining the first status and the second status indicate an alarm state, cause a workload assigned to a first data center associated with the first network node and the second network node to be reassigned to a second data center different from the first data center.
    Type: Application
    Filed: May 31, 2023
    Publication date: December 5, 2024
    Inventors: Akashdeep CHOPRA, Chandan Kumar SINGH, Ashish MADAN
  • Publication number: 20240403142
    Abstract: Ephemeral distributed locking in microservice systems is disclosed, A disclosed example system to manage microservices of a shared resource system includes interface circuitry, programmable circuitry, machine readable instructions to cause the programmable circuitry to: permit a first container to lock a microservice based on an annotation of the first container, the annotation corresponding to a request for utilization of locking semantics to lock the microservice, after the microservice is locked for use by the first container, prevent a second container requesting utilization of the locking semantics to lock the microservice based on the microservice being locked to the first container, and, after expiration of a time period, release the microservice from being locked for use by the first container.
    Type: Application
    Filed: August 9, 2023
    Publication date: December 5, 2024
    Inventors: AMIT MEENA, Ashish Agrawal, Priyanka Makode, Mandar Phatak, Ankit Bhartiya
  • Patent number: D1054023
    Type: Grant
    Filed: January 18, 2023
    Date of Patent: December 10, 2024
    Assignee: Alcon Inc.
    Inventors: Joel Cicchella, Grace Chuang Liao, James Y. Chon, Ashish Sinha