Patents by Inventor Ashita Mirchandani
Ashita Mirchandani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240113115Abstract: A semiconductor die includes: a silicon substrate; a trench gate NMOS transistor formed in a first device region of the silicon substrate; a trench gate PMOS transistor formed in a second device region of the silicon substrate and electrically connected to the trench gate NMOS transistor; and an isolation structure interposed between the first device region and the second device region. Methods of monolithically integrating the trench gate NMOS transistor and the trench gate PMOS transistor in the same semiconductor die are also described.Type: ApplicationFiled: September 30, 2022Publication date: April 4, 2024Inventors: Harsh Naik, Timothy Henson, Honghai He, Robert Haase, Ashita Mirchandani, Alireza Mojab
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Publication number: 20230307454Abstract: In an embodiment, a semiconductor device includes a vertical power FET for switching a load current, the power FET including a channel region of a first conductivity type and a first lateral FET and a second lateral FET providing an output stage of gate driver circuitry for driving the power FET. The first lateral FET includes a channel region of the first conductivity type and the second lateral FET includes a channel region of a second conductivity type opposing the first conductivity type. The power FET and the first and second lateral FETs are monolithically integrated into a semiconductor substrate of the first conductivity type and that has a first surface. A drain of the first lateral FET and a source of the second lateral FET are electrically coupled to a gate of the power FET.Type: ApplicationFiled: March 14, 2023Publication date: September 28, 2023Inventors: Honghai He, Robert Haase, Harsh Naik, Timothy Henson, Ashita Mirchandani
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Publication number: 20230307450Abstract: In an embodiment, a semiconductor device is provided that includes: a vertical power FET configured to switch a load current and provide a channel of a first conductivity type; and a lateral FET configured to drive the vertical power FET and provide a channel of a second conductivity type opposing the first conductivity type. The vertical power FET and the lateral FET are monolithically integrated into a semiconductor substrate of the first conductivity type and a drain of the lateral FET is electrically coupled to a gate of the vertical power FET.Type: ApplicationFiled: March 14, 2023Publication date: September 28, 2023Inventors: Harsh Naik, Timothy Henson, Ashita Mirchandani, Robert Haase, Honghai He
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Publication number: 20220231163Abstract: A method for manufacturing a semiconductor transistor device includes etching a vertical gate trench into a silicon region, depositing a silicon gate material on an interlayer dielectric formed in the vertical gate trench so that an upper side of the interlayer dielectric is covered, etching through the silicon gate material in the vertical gate trench to partly uncover the upper side of the interlayer dielectric and so that a silicon gate region of a gate electrode of the semiconductor transistor device remains in the vertical gate trench, and depositing a metal material into the vertical gate trench so that the partly uncovered upper side of the interlayer dielectric is covered by the metal material.Type: ApplicationFiled: April 6, 2022Publication date: July 21, 2022Inventors: Robert Paul Haase, Jyotshna Bhandari, Heimo Hofer, Ling Ma, Ashita Mirchandani, Harsh Naik, Martin Poelzl, Martin Henning Vielemeyer, Britta Wutte
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Patent number: 11316043Abstract: A transistor device with a gate electrode in a vertical gate trench is described. The gate electrode includes a silicon gate region and a metal inlay region. The silicon gate region forms at least a section of a sidewall of the gate electrode. The metal inlay region extends up from a lower end of the gate electrode.Type: GrantFiled: December 17, 2019Date of Patent: April 26, 2022Assignee: Infineon Technologies Austria AGInventors: Robert Paul Haase, Jyotshna Bhandari, Heimo Hofer, Ling Ma, Ashita Mirchandani, Harsh Naik, Martin Poelzl, Martin Henning Vielemeyer, Britta Wutte
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Publication number: 20220109068Abstract: A semiconductor device includes: a trench formed in a surface of a semiconductor substrate and extending lengthwise in a direction parallel to the surface; a body region adjoining the trench; a source region adjoining the trench above the body region; a drift region adjoining the trench below the body region; a field electrode in a lower part of the trench and separated from the substrate; and a gate electrode in an upper part of the trench and separated from the substrate and the field electrode. A first section of the field electrode is buried below the gate electrode in the trench. A second section of the field electrode transitions upward from the first section in a direction toward the surface. The separation between the second section and the gate electrode is greater than or equal to the separation between the first section and the gate electrode.Type: ApplicationFiled: December 16, 2021Publication date: April 7, 2022Inventors: Ashita Mirchandani, Robert Haase, Tim Henson, Ling Ma, Niraj Ranjan
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Patent number: 11217690Abstract: A semiconductor device includes: a trench formed in a surface of a semiconductor substrate and extending lengthwise in a direction parallel to the surface; a body region adjoining the trench; a source region adjoining the trench above the body region; a drift region adjoining the trench below the body region; a field electrode in a lower part of the trench and separated from the substrate; and a gate electrode in an upper part of the trench and separated from the substrate and the field electrode. A first section of the field electrode is buried below the gate electrode in the trench. A second section of the field electrode transitions upward from the first section in a direction toward the surface. The separation between the second section and the gate electrode is greater than or equal to the separation between the first section and the gate electrode.Type: GrantFiled: September 16, 2019Date of Patent: January 4, 2022Assignee: Infineon Technologies Austria AGInventors: Ashita Mirchandani, Robert Haase, Tim Henson, Ling Ma, Niraj Ranjan
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Patent number: 11158569Abstract: In an embodiment, a semiconductor package includes at least one die pad, a plurality of outer contacts, a first semiconductor device and a second semiconductor device. The second semiconductor device includes a first transistor device having a source electrode, a gate electrode, a drain electrode, a front surface, and a rear surface. A front metallization is positioned on the front surface and a rear metallization on the rear surface of the second semiconductor device. The front metallization includes a first power contact pad coupled to the source electrode and mounted on the at least one die pad. The rear metallization includes a second power contact pad electrically coupled to the drain electrode, and an auxiliary lateral redistribution structure electrically insulated from the second power contact pad and the drain electrode. The first semiconductor device is electrically coupled to the auxiliary lateral redistribution structure.Type: GrantFiled: February 26, 2020Date of Patent: October 26, 2021Assignees: Infineon Technologies Austria AG, Infineon Technologies Americas Corp.Inventors: Gerhard Noebauer, Ashita Mirchandani
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Publication number: 20210083096Abstract: A semiconductor device includes: a trench formed in a surface of a semiconductor substrate and extending lengthwise in a direction parallel to the surface; a body region adjoining the trench; a source region adjoining the trench above the body region; a drift region adjoining the trench below the body region; a field electrode in a lower part of the trench and separated from the substrate; and a gate electrode in an upper part of the trench and separated from the substrate and the field electrode. A first section of the field electrode is buried below the gate electrode in the trench. A second section of the field electrode transitions upward from the first section in a direction toward the surface. The separation between the second section and the gate electrode is greater than or equal to the separation between the first section and the gate electrode.Type: ApplicationFiled: September 16, 2019Publication date: March 18, 2021Inventors: Ashita Mirchandani, Robert Haase, Tim Henson, Ling Ma, Niraj Ranjan
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Publication number: 20200273788Abstract: In an embodiment, a semiconductor package includes at least one die pad, a plurality of outer contacts, a first semiconductor device and a second semiconductor device. The second semiconductor device includes a first transistor device having a source electrode, a gate electrode, a drain electrode, a front surface, and a rear surface. A front metallization is positioned on the front surface and a rear metallization on the rear surface of the second semiconductor device. The front metallization includes a first power contact pad coupled to the source electrode and mounted on the at least one die pad. The rear metallization includes a second power contact pad electrically coupled to the drain electrode, and an auxiliary lateral redistribution structure electrically insulated from the second power contact pad and the drain electrode. The first semiconductor device is electrically coupled to the auxiliary lateral redistribution structure.Type: ApplicationFiled: February 26, 2020Publication date: August 27, 2020Inventors: Gerhard Noebauer, Ashita Mirchandani
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Publication number: 20200203525Abstract: A transistor device with a gate electrode in a vertical gate trench is described. The gate electrode includes a silicon gate region and a metal inlay region. The silicon gate region forms at least a section of a sidewall of the gate electrode. The metal inlay region extends up from a lower end of the gate electrode.Type: ApplicationFiled: December 17, 2019Publication date: June 25, 2020Inventors: Robert Paul Haase, Jyotshna Bhandari, Heimo Hofer, Ling Ma, Ashita Mirchandani, Harsh Naik, Martin Poelzl, Martin Henning Vielemeyer, Britta Wutte
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Patent number: 10529845Abstract: In an embodiment, a semiconductor device includes a semiconductor body having a field effect transistor device with an active region and an edge termination region that surrounds the active region on all sides. The active region includes a first serpentine trench in the semiconductor body, a first field plate in the first serpentine trench, a second serpentine trench in the semiconductor body, and a second field plate in the second serpentine trench. The first serpentine trench is separate and laterally spaced apart from the second serpentine trench.Type: GrantFiled: March 9, 2018Date of Patent: January 7, 2020Assignee: Infineon Technologies Austria AGInventors: Ashita Mirchandani, Thomas Feil, Maximilian Roesch, Britta Wutte
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Publication number: 20190280117Abstract: In an embodiment, a semiconductor device includes a semiconductor body having a field effect transistor device with an active region and an edge termination region that surrounds the active region on all sides. The active region includes a first serpentine trench in the semiconductor body, a first field plate in the first serpentine trench, a second serpentine trench in the semiconductor body, and a second field plate in the second serpentine trench. The first serpentine trench is separate and laterally spaced apart from the second serpentine trench.Type: ApplicationFiled: March 9, 2018Publication date: September 12, 2019Inventors: Ashita Mirchandani, Thomas Feil, Maximilian Roesch, Britta Wutte
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Patent number: 9991377Abstract: According to an exemplary implementation, a field-effect transistor (FET) includes first and second gate trenches extending to a drift region of a first conductivity type. The FET also includes a base region of a second conductivity type that is situated between the first and second gate trenches. A ruggedness enhancement region is situated between the first and second gate trenches, where the ruggedness enhancement region is configured to provide an enhanced avalanche current path from a drain region to the base region when the FET is in an avalanche condition. The enhanced avalanche current path is away from the first and second gate trenches. The ruggedness enhancement region can be of the second conductivity type that includes a higher dopant concentration than the base region. Furthermore, the ruggedness enhancement region can be extending below the first and second gate trenches.Type: GrantFiled: March 11, 2013Date of Patent: June 5, 2018Assignee: Infineon Technologies Americas Corp.Inventors: Ashita Mirchandani, Timothy D. Henson, Ling Ma, Niraj Ranjan
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Patent number: 9673318Abstract: A semiconductor device includes a semiconductor substrate having a base region situated over a drift region, a source trench extending through the base region and into the drift region, the source trench having a shield electrode, a gate trench extending through the base region and into the drift region, the gate trench adjacent the source trench, the gate trench having a gate electrode situated above a buried electrode. The source trench is surrounded by the gate trench. The shield electrode is coupled to a source contact over the semiconductor substrate. The semiconductor device also includes a source region over the base region. The gate trench includes gate trench dielectrics lining a bottom and sidewalls of the gate trench. The source trench includes source trench dielectrics lining a bottom and sidewalls of the source trench.Type: GrantFiled: January 13, 2016Date of Patent: June 6, 2017Assignee: Infineon Technologies Americas Corp.Inventors: Ashita Mirchandani, Timothy D. Henson
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Publication number: 20130264636Abstract: According to an exemplary implementation, a field-effect transistor (FET) includes first and second gate trenches extending to a drift region of a first conductivity type. The FET also includes a base region of a second conductivity type that is situated between the first and second gate trenches. A ruggedness enhancement region is situated between the first and second gate trenches, where the ruggedness enhancement region is configured to provide an enhanced avalanche current path from a drain region to the base region when the FET is in an avalanche condition. The enhanced avalanche current path is away from the first and second gate trenches. The ruggedness enhancement region can be of the second conductivity type that includes a higher dopant concentration than the base region. Furthermore, the ruggedness enhancement region can be extending below the first and second gate trenches.Type: ApplicationFiled: March 11, 2013Publication date: October 10, 2013Applicant: International Rectifier CorporationInventors: Ashita Mirchandani, Timothy D. Henson, Ling Ma, Niraj Ranjan
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Patent number: 7557395Abstract: A trench power semiconductor device including a recessed termination structure.Type: GrantFiled: January 27, 2004Date of Patent: July 7, 2009Assignee: International Rectifier CorporationInventors: Ling Ma, Adam Amali, Siddharth Kiyawat, Ashita Mirchandani, Donald He, Naresh Thapar, Ritu Sodhi, Kyle Spring, Daniel Kinzer
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Patent number: 6921699Abstract: A process for manufacturing a semiconductor device of the trench variety with reduced feature sizes and improved characteristics which process includes forming a termination structure having a field oxide disposed in a recess below the surface of the semiconductor die in which the active elements of the device are formed, and forming source regions after the major thermal steps have been performed.Type: GrantFiled: September 29, 2003Date of Patent: July 26, 2005Assignee: International Rectifier CorporationInventors: Ling Ma, Adam Amali, Siddharth Kiyawat, Ashita Mirchandani, Donald He, Naresh Thapar, Ritu Sodhi, Kyle Spring, Daniel Kinzer
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Publication number: 20040251491Abstract: A trench power semiconductor device including a recessed termination structure.Type: ApplicationFiled: January 27, 2004Publication date: December 16, 2004Inventors: Ling Ma, Adam Amali, Siddharth Kiyawat, Ashita Mirchandani, Donald He, Naresh Thapar, Ritu Sodhi, Kyle Spring, Daniel Kinzer
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Publication number: 20040137684Abstract: A process for manufacturing a semiconductor device of the trench variety with reduced feature sizes and improved characteristics which process includes forming a termination structure having a field oxide disposed in a recess below the surface of the semiconductor die in which the active elements of the device are formed, and forming source regions after the major thermal steps have been performed.Type: ApplicationFiled: September 29, 2003Publication date: July 15, 2004Inventors: Ling Ma, Adam Amali, Siddharth Kiyawat, Ashita Mirchandani, Donald He, Naresh Thapar, Ritu Sodhi, Kyle Spring, Daniel Kinzer