Patents by Inventor Ashita Mirchandani

Ashita Mirchandani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210083096
    Abstract: A semiconductor device includes: a trench formed in a surface of a semiconductor substrate and extending lengthwise in a direction parallel to the surface; a body region adjoining the trench; a source region adjoining the trench above the body region; a drift region adjoining the trench below the body region; a field electrode in a lower part of the trench and separated from the substrate; and a gate electrode in an upper part of the trench and separated from the substrate and the field electrode. A first section of the field electrode is buried below the gate electrode in the trench. A second section of the field electrode transitions upward from the first section in a direction toward the surface. The separation between the second section and the gate electrode is greater than or equal to the separation between the first section and the gate electrode.
    Type: Application
    Filed: September 16, 2019
    Publication date: March 18, 2021
    Inventors: Ashita Mirchandani, Robert Haase, Tim Henson, Ling Ma, Niraj Ranjan
  • Publication number: 20200273788
    Abstract: In an embodiment, a semiconductor package includes at least one die pad, a plurality of outer contacts, a first semiconductor device and a second semiconductor device. The second semiconductor device includes a first transistor device having a source electrode, a gate electrode, a drain electrode, a front surface, and a rear surface. A front metallization is positioned on the front surface and a rear metallization on the rear surface of the second semiconductor device. The front metallization includes a first power contact pad coupled to the source electrode and mounted on the at least one die pad. The rear metallization includes a second power contact pad electrically coupled to the drain electrode, and an auxiliary lateral redistribution structure electrically insulated from the second power contact pad and the drain electrode. The first semiconductor device is electrically coupled to the auxiliary lateral redistribution structure.
    Type: Application
    Filed: February 26, 2020
    Publication date: August 27, 2020
    Inventors: Gerhard Noebauer, Ashita Mirchandani
  • Publication number: 20200203525
    Abstract: A transistor device with a gate electrode in a vertical gate trench is described. The gate electrode includes a silicon gate region and a metal inlay region. The silicon gate region forms at least a section of a sidewall of the gate electrode. The metal inlay region extends up from a lower end of the gate electrode.
    Type: Application
    Filed: December 17, 2019
    Publication date: June 25, 2020
    Inventors: Robert Paul Haase, Jyotshna Bhandari, Heimo Hofer, Ling Ma, Ashita Mirchandani, Harsh Naik, Martin Poelzl, Martin Henning Vielemeyer, Britta Wutte
  • Patent number: 10529845
    Abstract: In an embodiment, a semiconductor device includes a semiconductor body having a field effect transistor device with an active region and an edge termination region that surrounds the active region on all sides. The active region includes a first serpentine trench in the semiconductor body, a first field plate in the first serpentine trench, a second serpentine trench in the semiconductor body, and a second field plate in the second serpentine trench. The first serpentine trench is separate and laterally spaced apart from the second serpentine trench.
    Type: Grant
    Filed: March 9, 2018
    Date of Patent: January 7, 2020
    Assignee: Infineon Technologies Austria AG
    Inventors: Ashita Mirchandani, Thomas Feil, Maximilian Roesch, Britta Wutte
  • Publication number: 20190280117
    Abstract: In an embodiment, a semiconductor device includes a semiconductor body having a field effect transistor device with an active region and an edge termination region that surrounds the active region on all sides. The active region includes a first serpentine trench in the semiconductor body, a first field plate in the first serpentine trench, a second serpentine trench in the semiconductor body, and a second field plate in the second serpentine trench. The first serpentine trench is separate and laterally spaced apart from the second serpentine trench.
    Type: Application
    Filed: March 9, 2018
    Publication date: September 12, 2019
    Inventors: Ashita Mirchandani, Thomas Feil, Maximilian Roesch, Britta Wutte
  • Patent number: 9991377
    Abstract: According to an exemplary implementation, a field-effect transistor (FET) includes first and second gate trenches extending to a drift region of a first conductivity type. The FET also includes a base region of a second conductivity type that is situated between the first and second gate trenches. A ruggedness enhancement region is situated between the first and second gate trenches, where the ruggedness enhancement region is configured to provide an enhanced avalanche current path from a drain region to the base region when the FET is in an avalanche condition. The enhanced avalanche current path is away from the first and second gate trenches. The ruggedness enhancement region can be of the second conductivity type that includes a higher dopant concentration than the base region. Furthermore, the ruggedness enhancement region can be extending below the first and second gate trenches.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: June 5, 2018
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Ashita Mirchandani, Timothy D. Henson, Ling Ma, Niraj Ranjan
  • Patent number: 9673318
    Abstract: A semiconductor device includes a semiconductor substrate having a base region situated over a drift region, a source trench extending through the base region and into the drift region, the source trench having a shield electrode, a gate trench extending through the base region and into the drift region, the gate trench adjacent the source trench, the gate trench having a gate electrode situated above a buried electrode. The source trench is surrounded by the gate trench. The shield electrode is coupled to a source contact over the semiconductor substrate. The semiconductor device also includes a source region over the base region. The gate trench includes gate trench dielectrics lining a bottom and sidewalls of the gate trench. The source trench includes source trench dielectrics lining a bottom and sidewalls of the source trench.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: June 6, 2017
    Assignee: Infineon Technologies Americas Corp.
    Inventors: Ashita Mirchandani, Timothy D. Henson
  • Publication number: 20130264636
    Abstract: According to an exemplary implementation, a field-effect transistor (FET) includes first and second gate trenches extending to a drift region of a first conductivity type. The FET also includes a base region of a second conductivity type that is situated between the first and second gate trenches. A ruggedness enhancement region is situated between the first and second gate trenches, where the ruggedness enhancement region is configured to provide an enhanced avalanche current path from a drain region to the base region when the FET is in an avalanche condition. The enhanced avalanche current path is away from the first and second gate trenches. The ruggedness enhancement region can be of the second conductivity type that includes a higher dopant concentration than the base region. Furthermore, the ruggedness enhancement region can be extending below the first and second gate trenches.
    Type: Application
    Filed: March 11, 2013
    Publication date: October 10, 2013
    Applicant: International Rectifier Corporation
    Inventors: Ashita Mirchandani, Timothy D. Henson, Ling Ma, Niraj Ranjan
  • Patent number: 7557395
    Abstract: A trench power semiconductor device including a recessed termination structure.
    Type: Grant
    Filed: January 27, 2004
    Date of Patent: July 7, 2009
    Assignee: International Rectifier Corporation
    Inventors: Ling Ma, Adam Amali, Siddharth Kiyawat, Ashita Mirchandani, Donald He, Naresh Thapar, Ritu Sodhi, Kyle Spring, Daniel Kinzer
  • Patent number: 6921699
    Abstract: A process for manufacturing a semiconductor device of the trench variety with reduced feature sizes and improved characteristics which process includes forming a termination structure having a field oxide disposed in a recess below the surface of the semiconductor die in which the active elements of the device are formed, and forming source regions after the major thermal steps have been performed.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: July 26, 2005
    Assignee: International Rectifier Corporation
    Inventors: Ling Ma, Adam Amali, Siddharth Kiyawat, Ashita Mirchandani, Donald He, Naresh Thapar, Ritu Sodhi, Kyle Spring, Daniel Kinzer
  • Publication number: 20040251491
    Abstract: A trench power semiconductor device including a recessed termination structure.
    Type: Application
    Filed: January 27, 2004
    Publication date: December 16, 2004
    Inventors: Ling Ma, Adam Amali, Siddharth Kiyawat, Ashita Mirchandani, Donald He, Naresh Thapar, Ritu Sodhi, Kyle Spring, Daniel Kinzer
  • Publication number: 20040137684
    Abstract: A process for manufacturing a semiconductor device of the trench variety with reduced feature sizes and improved characteristics which process includes forming a termination structure having a field oxide disposed in a recess below the surface of the semiconductor die in which the active elements of the device are formed, and forming source regions after the major thermal steps have been performed.
    Type: Application
    Filed: September 29, 2003
    Publication date: July 15, 2004
    Inventors: Ling Ma, Adam Amali, Siddharth Kiyawat, Ashita Mirchandani, Donald He, Naresh Thapar, Ritu Sodhi, Kyle Spring, Daniel Kinzer