Abstract: A data processing system operable to process a neural network, and comprising a plurality of processors. The data processing system is operable to determine whether to perform neural network processing using a single processor or using plural processors. When it is determined that plural processors should be used, a distribution of the neural network processing among two or more of the processors is determined and the two or more processors are each assigned a portion of the neural network processing to perform. A neural network processing output is provided as a result of the processors performing their assigned portions of the neural network processing.

Abstract: A data processing system operable to process a neural network, and comprising a plurality of processors. The data processing system is operable to determine whether to perform neural network processing using a single processor or using plural processors. When it is determined that plural processors should be used, a distribution of the neural network processing among two or more of the processors is determined and the two or more processors are each assigned a portion of the neural network processing to perform. A neural network processing output is provided as a result of the processors performing their assigned portions of the neural network processing.

Abstract: A data processing apparatus having an interconnect circuit operable to transfer snoop messages between a plurality of connected devices, at least one of which has multiple ports each coupled to a local cache. The interconnect circuit has decode logic that identifies, from an address in a snoop message, which port is coupled to the local cache associated with the address, and the interconnect circuit transmits the snoop message to that port. The interconnect circuit may also have a snoop filter that stores a snoop vector for each block of data in the local caches. Each snoop vector has an address tag that identifies the block of data and a presence vector indicative of which devices of the connected devices have a copy of the block of data. The presence vector does not identify which port of a device has access to the copy.

Abstract: Circuitry for receiving transaction requests from a plurality of masters and the masters themselves are disclosed. The circuitry comprises: an input port for receiving said transaction requests, at least one of said transaction requests received comprising an indicator indicating if said transaction is a speculative transaction; an output port for outputting a response to said master said transaction request was received from; and transaction control circuitry; wherein said transaction control circuitry is responsive to a speculative transaction request to determine a state of at least a portion of a data processing apparatus said circuitry is operating within and in response to said state being a predetermined state said transaction control circuitry generates a transaction cancel indicator and outputs said transaction cancel indicator as said response, said transaction cancel indicator indicating to said master that said speculative transaction will not be performed.

Abstract: An integrated circuit 300 includes a functional circuit 310 and a diagnostic circuit 330. The integrated circuit includes a signal interface controller 320 operable to monitor a signal associated with at least one of the functional circuit and the diagnostic circuit to control selective communication of a diagnostic signal and a functional signal for communication across a signal interface in dependence upon the monitored signal. A further integrated circuit has a signal interface providing a communication path and communicates a functional signal having at least one multi-bit value in which at least one bit is replaced by data of a diagnostic signal.

Abstract: An integrated circuit 300 includes a functional circuit 310 and a diagnostic circuit 330. The integrated circuit includes a signal interface controller 320 operable to monitor a signal associated with at least one of the functional circuit and the diagnostic circuit to control selective communication of a diagnostic signal and a functional signal for communication across a signal interface in dependence upon the monitored signal. A further integrated circuit has a signal interface providing a communication path and communicates a functional signal having at least one multi-bit value in which at least one bit is replaced by data of a diagnostic signal.

Abstract: An integrated circuit 300 includes a functional circuit 310 and a diagnostic circuit 330. The integrated circuit includes a signal interface controller 320 operable to monitor a signal associated with at least one of the functional circuit and the diagnostic circuit to control selective communication of a diagnostic signal and a functional signal for communication across a signal interface in dependence upon the monitored signal. A further integrated circuit has a signal interface providing a communication path and communicates a functional signal having at least one multi-bit value in which at least one bit is replaced by data of a diagnostic signal.

Abstract: A data processing apparatus and method are provided for controlling access to memory. The data processing apparatus comprises main processing logic operable to execute a sequence of instructions in order to perform a process, and subsidiary processing logic operable to perform at least part of the process on behalf of the main processing logic. A memory is provided that is accessible by the main processing logic when performing the process, the main processing logic defining a portion of the memory to be allocated memory accessible to the subsidiary processing logic when performing part of the process on behalf of the main processing logic. Further, a memory management unit is provided that is programmable by the main processing logic and operable to control access to the allocated memory by the subsidiary processing logic.

Abstract: A data processing system is provided with a general purpose programmable processor and an accelerator processor. Coherency control circuitry manages data coherence between data items which may be stored within a cache memory and/or a further memory. Memory access requests from the accelerator processor are received by a memory request switching circuitry which is responsive to a signal from the accelerator processor to direct the memory access request either via coherency control circuit or directly to the further memory.

Abstract: A data processing system 2 is provided with a general purpose programmable processor 4 and an accelerator processor 6. Coherency control circuitry 20 manages data coherence between data items which may be stored within a cache memory 16 and/or a further memory 18. Memory access requests from the accelerator processor 6 are received by a memory request switching circuitry 22 which is responsive to a signal from the accelerator processor 6 to direct the memory access request either via coherency control circuit 20 or directly to the further memory 18.

Abstract: Circuitry for receiving transaction requests from a plurality of masters and the masters themselves are disclosed. The circuitry comprises: an input port for receiving said transaction requests, at least one of said transaction requests received comprising an indicator indicating if said transaction is a speculative transaction; an output port for outputting a response to said master said transaction request was received from; and transaction control circuitry; wherein said transaction control circuitry is responsive to a speculative transaction request to determine a state of at least a portion of a data processing apparatus said circuitry is operating within and in response to said state being a predetermined state said transaction control circuitry generates a transaction cancel indicator and outputs said transaction cancel indicator as said response, said transaction cancel indicator indicating to said master that said speculative transaction will not be performed.

Abstract: A memory controller for controlling access to a memory, said memory comprising at least one memory array, said at least one memory array comprising a plurality of rows and a plurality of columns, access to an element within said memory array being performed by opening a row comprising said element and then accessing a column comprising said element, said at least one memory array being adapted to have no more than one row in said at least one memory array open at a time; said memory controller being responsive to a memory access request to access an element within said memory and following said access to determine if said row comprising said accessed element should be closed or should remain open in dependence upon a property of said memory access request.

Abstract: The present invention provides a data processing apparatus and method for merging secure and non-secure data. The apparatus comprises at least one processor operable to execute a non-secure process to produce non-secure data to be included in an output data stream, and to execute a secure process to produce secure data to be included in the output data stream. A non-secure buffer is provided for receiving the non-secure data produced by the non-secure process, and in addition a secure buffer is provided for receiving the secure data produced by the secure process, the secure buffer not being accessible by the non-secure process. An output controller is then arranged to read the non-secure data from the non-secure buffer and the secure data from the secure buffer, and to merge the non-secure data and the secure data in order to produce a combined data stream, the output data stream then being derivable from the combined data stream.

Abstract: A data processing system is provided for setting a value of a performance controlling parameter during processing of a data stream comprising a plurality of data blocks. The performance controlling parameter is set by deriving a complexity measure for at least one data block by performing an initial processing stage on the at least one data block. The performance controlling parameter is set to a predicted value in dependence upon the complexity measure and at least one further processing stage is performed on the at least one data block at the predicted value of the performance controlling parameter.

Abstract: An integrated circuit 300 includes a functional circuit 320 and a diagnostic circuit 330. The integrated circuit comprises a signal interface controller 320 operable to monitor a signal associated with at least one of the functional circuit and the diagnostic circuit to control selective communication of a diagnostic signal and a functional signal for communication across a signal interface in dependence upon the monitored signal. A further integrated circuit has a signal interface providing a communication path and communicates a functional signal having at least one multi-bit value in which at least one bit is replaced by data of a diagnostic signal.

Abstract: The present invention provides a logic unit and integrated circuit for clearing interrupts. The logic unit is coupled to a bus operating in a first clock domain, and is arranged to interface between the bus and a device operating in a second clock domain, the frequency of the second clock domain being less than the frequency of the first clock domain. In accordance with the present invention, the logic unit comprises an interrupt source, responsive to a signal issued by the device, to assert a first interrupt signal in the second clock domain, and output logic, responsive to the first interrupt signal-to output a second interrupt signal via the bus to a processor operating in the first clock domain. The processor is arranged to process the interrupt indicated by the second interrupt signal, and to issue a clear request signal at a predetermined point during processing of the interrupt.

Abstract: The present invention provides a logic unit and integrated circuit for clearing interrupts. The logic unit is coupled to a bus operating in a first clock domain, and is arranged to interface between the bus and a device operating in a second clock domain, the frequency of the second clock domain being less than the frequency of the first clock domain. In accordance with the present invention, the logic unit comprises an interrupt source, responsive to a signal issued by the device, to assert a first interrupt signal in the second clock domain, and output logic, responsive to the first interrupt signal to output a second interrupt signal via the bus to a processor operating in the first clock domain. The processor is arranged to process the interrupt indicated by the second interrupt signal, and to issue a clear request signal at a predetermined point during processing of the interrupt.

Abstract: A display palette system comprising a digital palette 16 supplied with frames of data 26. Each frame of data 26 includes a complete set of palette mapping data and control data 28 with which the digital palette 16 is programmed under control of a palette control circuit 24. The rows of logical pixel data that follow in the frame each terminate with row palette data RP that can be directed to reprogram the digital palette 16 part of the way through the display of a single frame.

Abstract: The present invention provides an integrated circuit comprising a system bus to which a processor is connectable, and first and second peripheral buses to which peripheral units used by said processor are connected, the first peripheral bus operating at a higher clock speed than the second peripheral bus. Further, the integrated circuit comprises bridge logic for providing an interface between the system bus and the peripheral buses to enable signals to be passed between the system bus and the peripheral buses, the bridge logic comprising clock resynchronisation logic for synchronising the system bus and the peripheral buses.Through the provision of first and second peripheral buses operating at different clock speeds, the integrated circuit of the present invention provides a great deal of flexibility for reducing the power consumption of the integrated circuit as compared with a similar integrated circuit having only one peripheral bus.