Patents by Inventor Ashok C. Patrawala

Ashok C. Patrawala has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Low power true/complement driver
    Patent number: 4130768
    Abstract: The prior art, low power ratioless true/complement driver is improved upon by connecting a first isolation FET (T2) so that its gate is connected to drain potential (V.sub.DD) and by connecting to the second isolation FET (T4) so that its gate is connected to the phase-splitting node (1). This enables the number of clock pulse sources necessary to operate the generator circuit to be reduced by one so that the speed of the generator circuit is increased, by virtue of the second isolation FET (T4) having a gate size substantially smaller than the gate size of the inverting FET (T3) so that it will more rapidly switch from its on-state to its off-state than does the inverting FET.
    Type: Grant
    Filed: August 31, 1977
    Date of Patent: December 19, 1978
    Assignee: International Business Machines Corporation
    Inventors: John Bula, Ashok C. Patrawala