Abstract: A semiconductor power device includes a drift region of a first conductivity type, a well region extending above the drift region and having a second conductivity type opposite the first conductivity type, an active trench extending through the well region and into the drift region, source regions having the first conductivity type formed in the well region adjacent the active trench, and a first termination trench extending below the well region and disposed at an outer edge of an active region of the device. The sidewalls and bottom of the active trench are lined with dielectric material, and substantially filled with a first conductive layer forming an upper electrode and a second conductive layer forming a lower electrode, the upper electrode being disposed above the lower electrode and separated therefrom by inter-electrode dielectric material.

Abstract: Semiconductor devices and methods for making such devices that contain a 3D channel architecture are described. The 3D channel architecture is formed using a dual trench structure containing with a plurality of lower trenches extending in an x and y directional channels and separated by a mesa and an upper trench extending in a y direction and located in an upper portion of the substrate proximate a source region. Thus, smaller pillar trenches are formed within the main line-shaped trench. Such an architecture generates additional channel regions which are aligned substantially perpendicular to the conventional line-shaped channels. The channel regions, both conventional and perpendicular, are electrically connected by their corner and top regions to produce higher current flow in all three dimensions. With such a configuration, higher channel density, a stronger inversion layer, and a more uniform threshold distribution can be obtained for the semiconductor device. Other embodiments are described.

Abstract: A field effect transistor includes a plurality of trenches extending into a semiconductor region of a first conductivity type. The plurality of trenches include a plurality of gated trenches and a plurality of non-gated trenches. A body region of a second conductivity extends in the semiconductor region between adjacent trenches. A dielectric material fills a bottom portion of each of the gated and non-gated trenches. A gate electrode is disposed in each gated trench. A conductive material of the second conductivity type is disposed in each non-gated trench such that the conductive material and contacts corresponding body regions along sidewalls of the non-gated trench.

Abstract: In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor.

Abstract: A field effect transistor is disclosed. In one embodiment, the field effect transistor includes a trench extending into a drift region of the field effect transistor. A shield electrode in a lower portion of the trench is insulated from the drift region by a shield dielectric. A gate electrode in the trench over the shield electrode is insulated from the shield electrode by an inter-electrode dielectric. A source region is formed adjacent the trench. A resistive element is coupled to the shield electrode and to a source region in the field effective transistor.

Abstract: A method of forming a charge balance MOSFET includes the following steps. A substrate with an overlying epitaxial layer both of a first conductivity type, are provided. A gate trench extending through the epitaxial layer and terminating within the substrate is formed. A shield dielectric lining sidewalls and bottom surface of the gate trench is formed. A shield electrode is formed in the gate trench. A gate dielectric layer is formed along upper sidewalls of the gate trench. A gate electrode is formed in the gate trench such that the gate electrode extends over but is insulated from the shield electrode. A deep dimple extending through the epitaxial layer and terminating within the substrate is formed such that the deep dimple is laterally spaced from the gate trench. The deep dimple is filled with silicon material of the second conductivity type.

Abstract: In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the substrate. A body region of a second conductivity type silicon is formed such that a junction is formed between the body region and the substrate cap region. A trench extending through at least the body region is then formed. A source region of the first conductivity type is then formed in an upper portion of the body region. An out-diffusion region of the first conductivity type is formed in a lower portion of the body region as a result of one or more temperature cycles such that a spacing between the source region and the out-diffusion region defines a channel length of the field effect transistor.

Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Abstract: Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Abstract: A method of forming a monolithically integrated trench FET and Schottky diode includes the following steps. Two trenches are formed extending through an upper silicon layer and terminating within a lower silicon layer. The upper and lower silicon layers have a first conductivity type. First and second silicon regions of a second conductivity type are formed in the upper silicon layer between the pair of trenches. A third silicon region of the first conductivity type is formed extending into the first and second silicon regions between the pair of trenches such that remaining lower portions of the first and second silicon regions form two body regions separated by a portion of the upper silicon layer. A silicon etch is performed to form a contact opening extending through the first silicon region such that outer portions of the first silicon region remain, the outer portions forming source regions.

Abstract: A method of forming a charge balance MOSFET includes the following steps. A substrate with an overlying epitaxial layer both of a first conductivity type, are provided. A gate trench extending through the epitaxial layer and terminating within the substrate is formed. A shield dielectric lining sidewalls and bottom surface of the gate trench is formed. A shield electrode is formed in the gate trench. A gate dielectric layer is formed along upper sidewalls of the gate trench. A gate electrode is formed in the gate trench such that the gate electrode extends over but is insulated from the shield electrode. A deep dimple extending through the epitaxial layer and terminating within the substrate is formed such that the deep dimple is laterally spaced from the gate trench. The deep dimple is filled with silicon material of the second conductivity type.

Abstract: Various embodiments for improved power devices as well as their methods of manufacture, packaging and circuitry incorporating the same for use in a wide variety of power electronic applications are disclosed. One aspect of the invention combines a number of charge balancing techniques and other techniques for reducing parasitic capacitance to arrive at different embodiments for power devices with improved voltage performance, higher switching speed, and lower on-resistance. Another aspect of the invention provides improved termination structures for low, medium and high voltage devices. Improved methods of fabrication for power devices are provided according to other aspects of the invention. Improvements to specific processing steps, such as formation of trenches, formation of dielectric layers inside trenches, formation of mesa structures and processes for reducing substrate thickness, among others, are presented.

Abstract: A semiconductor region with an epitaxial layer extending over the semiconductor region is provided. A first silicon etch is performed to form an upper trench portion extending into and terminating within the epitaxial layer. A protective material is formed extending along sidewalls of the upper trench portion and over mesa regions adjacent the upper trench portion but not along a bottom surface of the upper trench portion. A second silicon etch is performed to form a lower trench portion extending from the bottom surface of the upper trench portion through the epitaxial layer and terminating within the semiconductor region, such that the lower trench portion is narrower than the upper trench portion.

Abstract: A semiconductor region with an epitaxial layer extending over the semiconductor region is provided. A first silicon etch is performed to form an upper trench portion extending into and terminating within the epitaxial layer. A protective material is formed extending along sidewalls of the upper trench portion and over mesa regions adjacent the upper trench portion but not along a bottom surface of the upper trench portion. A second silicon etch is performed to form a lower trench portion extending from the bottom surface of the upper trench portion through the epitaxial layer and terminating within the semiconductor region, such that the lower trench portion is narrower than the upper trench portion.

Abstract: A trench is formed in a semiconductor region. A dielectric layer lining sidewalls and bottom surface of the trench is formed. The dielectric layer is thicker along lower sidewalls and the bottom surface than along upper sidewalls of the trench. After forming the dielectric layer, a lower portion of the trench is filled with a shield electrode. Dielectric spacers are formed along the upper trench sidewalls. After forming the dielectric spacers, an inter-electrode dielectric (IED) is formed in the trench over the shield electrode. After forming the IED, the dielectric spacers are removed.

Abstract: A FET includes a trench in a semiconductor region. The trench has a lower portion with a shield electrode therein, and an upper portion with a gate electrode therein, where the upper portion is wider than the lower portion. The semiconductor region includes a substrate of a first conductivity type and a first silicon region of a second conductivity type over the substrate. The first silicon region has a first portion extending to a depth intermediate top and bottom surfaces of the gate electrode. The first silicon region has a second portion extending to a depth intermediate top and bottom surfaces of the shield electrode. The semiconductor region further includes a second silicon region of the first conductivity type between the lower trench portion and the second portion of the first silicon region that has a laterally-graded doping concentration decreasing in a direction away from the sidewalls of the lower trench portion.

Abstract: A method of forming a monolithically integrated trench FET and Schottky diode includes the following steps. Two trenches are formed extending through an upper silicon layer and terminating within a lower silicon layer. The upper and lower silicon layers have a first conductivity type. First and second silicon regions of a second conductivity type are formed in the upper silicon layer between the pair of trenches. A third silicon region of the first conductivity type is formed extending into the first and second silicon regions between the pair of trenches such that remaining lower portions of the first and second silicon regions form two body regions separated by a portion of the upper silicon layer. A silicon etch is performed to form a contact opening extending through the first silicon region such that outer portions of the first silicon region remain, the outer portions forming source regions.

Abstract: A method for forming a FET includes the following steps. Trenches are formed in a semiconductor region of a first conductivity type. A well region of a second conductivity type is formed in the semiconductor region. Source regions of the first conductivity type are formed in the well region such that channel regions defined by a spacing between the source regions and a bottom surface of the well region are formed in the well region along opposing sidewalls of the trenches. A gate dielectric layer having a non-uniform thickness is formed along the opposing sidewalls of the trenches such that a variation in thickness of the gate dielectric layer along at least a lower portion of the channel regions is: (i) substantially linear, and (ii) inversely dependent on a variation in doping concentration in the lower portion of the channel regions. A gate electrode is formed in each trench.

Abstract: A monolithically integrated trench FET and Schottky diode includes a pair of trenches terminating in a first silicon region of first conductivity type. Two body regions of a second conductivity type separated by a second silicon region of the first conductivity type are located between the pair of trenches. A source region of the first conductivity type is located over each body region. A contact opening extends between the pair of trenches to a depth below the source regions. An interconnect layer fills the contact opening so as to electrically contact the source regions and the second silicon region. Where the interconnect layer electrically contacts the second silicon region, a Schottky contact is formed.