Patents by Inventor Ashok Kumar JYANI

Ashok Kumar JYANI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11422599
    Abstract: The present disclosure provides a system and method for soft start scheme to control inrush current for VCONN in USB-C interface. The system includes: a serial shift register having flip-flops and adapted to obtain clock with programmable clock divider, frequency of clock changes dynamically by programming programmable clock divider; a resistor DAC unit configured to increment voltage in step-wise manner; a pass gate switch comprising NMOS gate switch and a PMOS gate switch connected in parallel and operatively coupled to the resistor DAC unit and configured to control an input voltage to a VCONN charge pump, said input voltage being in incremental steps such that the VCONN charge pump pumps an output voltage; and a VCONN switch gate operatively coupled to the VCONN charge pump and configured to supply the output voltage in controlled, incremental steps, such that the output voltage is ramped slowly to control the inrush current.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: August 23, 2022
    Assignee: SILICONCH SYSTEMS PVT LTD
    Inventors: Ashok Kumar Jyani, Satish Anand Verkila, Shubham Paliwal, Rakesh Kumar Polasa
  • Patent number: 11226664
    Abstract: Systems and methods for providing VCONN to configuration channel line in USB-interface, involving a sense switch and a VCONN switch coupled with the VCONN supply and a gate control unit; an over current protection (OCP) reference current unit configured to provide a predetermined current through the sense branch; a preamplifier configured to amplify a differential voltage between source terminal voltages of the sense switch and the VCONN switch; an Over Current detection comparator configured to generate an Over Current fault signal when the source terminal voltage at the VCONN switch is lower than the source terminal voltage at the sense switch; and a control unit configured to: activate, upon receipt of the generated Over Current fault signal, the gate control unit, wherein the gate control unit, upon activation, is configured to disable the sense switch and the VCONN switch respectively to protect the VCONN and CC_P from over current.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: January 18, 2022
    Assignee: SILICONCH SYSTEMS PVT LTD
    Inventors: Ashok Kumar Jyani, Satish Anand Verkila, Shubham Paliwal
  • Publication number: 20210303049
    Abstract: The present disclosure provides a system and method for soft start scheme to control inrush current for VCONN in USB-C interface. The system includes: a serial shift register having flip-flops and adapted to obtain clock with programmable clock divider, frequency of clock changes dynamically by programming programmable clock divider; a resistor DAC unit configured to increment voltage in step-wise manner; a pass gate switch comprising NMOS gate switch and a PMOS gate switch connected in parallel and operatively coupled to the resistor DAC unit and configured to control an input voltage to a VCONN charge pump, said input voltage being in incremental steps such that the VCONN charge pump pumps an output voltage; and a VCONN switch gate operatively coupled to the VCONN charge pump and configured to supply the output voltage in controlled, incremental steps, such that the output voltage is ramped slowly to control the inrush current.
    Type: Application
    Filed: June 29, 2020
    Publication date: September 30, 2021
    Inventors: Ashok Kumar JYANI, Satish Anand VERKILA, Shubham PALIWAL, Rakesh Kumar POLASA
  • Publication number: 20210303048
    Abstract: Systems and methods for providing VCONN to configuration channel line in USB-interface, involving a sense switch and a VCONN switch coupled with the VCONN supply and a gate control unit; an over current protection (OCP) reference current unit configured to provide a predetermined current through the sense branch; a preamplifier configured to amplify a differential voltage between source terminal voltages of the sense switch and the VCONN switch; an Over Current detection comparator configured to generate an Over Current fault signal when the source terminal voltage at the VCONN switch is lower than the source terminal voltage at the sense switch; and a control unit configured to: activate, upon receipt of the generated Over Current fault signal, the gate control unit, wherein the gate control unit, upon activation, is configured to disable the sense switch and the VCONN switch respectively to protect the VCONN and CC_P from over current.
    Type: Application
    Filed: June 22, 2020
    Publication date: September 30, 2021
    Inventors: Ashok Kumar JYANI, Satish Anand VERKILA, Shubham PALIWAL