Patents by Inventor Ashok N. Kabadi

Ashok N. Kabadi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10198333
    Abstract: An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test.
    Type: Grant
    Filed: December 23, 2010
    Date of Patent: February 5, 2019
    Assignee: INTEL CORPORATION
    Inventors: Mark B. Trobough, Keshavan K. Tiruvallur, Chinna B. Prudvi, Christian E. Iovin, David W. Grawrock, Jay J. Nejedlo, Ashok N. Kabadi, Travis K. Goff, Evan J. Halprin, Kapila B. Udawatta, Jiun Long Foo, Wee Hoo Cheah, Vui Yong Liew, Selvakumar Raja Gopal, Yuen Tat Lee, Samie B. Samaan, Kip C. Killpack, Neil Dobler, Nagib Z. Hakim, Brian Meyer, William H. Penner, John L. Baudrexl, Russell J. Wunderlich, James J. Grealish, Kyle Markley, Timothy S. Storey, Loren J. McConnell, Lyle E. Cool, Mukesh Kataria, Rahima K. Mohammed, Tieyu Zheng, Yi Amy Xia, Ridvan A. Sahan, Arun R. Ramadorai, Priyadarsan Patra, Edwin E. Parks, Abhijit Davare, Padmakumar Gopal, Bruce Querbach, Hermann W. Gartler, Keith Drescher, Sanjay S. Salem, David C. Florey
  • Publication number: 20150127983
    Abstract: An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and de-bug of a part/platform under test.
    Type: Application
    Filed: December 23, 2010
    Publication date: May 7, 2015
    Applicant: INTEL CORPORATION
    Inventors: Mark B. Trobough, Keshavan K. Tiruvallur, Chinna B. Prudvi, Christian E. Iovin, David W. Grawrock, Jay J. Nejedlo, Ashok N. Kabadi, Travis K. Goff, Evan J. Halprin, Kapila B. Udawatta, Jiun Long Foo, Wee Hoo Cheah, Vui Yong Liew, Selvakumar Raja Gopal, Yuen Tat Lee, Samie B. Samaan, Kip C. Killpack, Neil Dobler, Nagib Z. Hakim, Briar Meyer, William H. Penner, John L. Baudrexl, Russell J. Wunderlich, James J. Grealish, Kyle Markley, Timothy S. Storey, Loren J. McConnell, Lyle E. Cool, Mukesh Kataria, Rahima K. Mohammed, Tieyu Zheng, Yi Amy Xia, Ridvan A. Sahan, Arun R. Ramadorai, Priyadarsan Patra, Edwin E. Parks, Abhijit Davare, Padmakumar Gopal, Bruce Querbach, Hermann W. Gartler, Keith Drescher, Sanjay S. Salem, David C. Florey
  • Patent number: 7177142
    Abstract: The apparatus and method described herein are for coupling an integrated circuit to a circuit board, while eliminating the need for a backing plate, when a compression socket is utilized. A plurality of tension pins are coupled to an integrated circuit for engaging a plurality of corresponding barrels in a circuit board to compress a compression socket to make an electrical connection between the integrated circuit and the circuit board.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: February 13, 2007
    Assignee: Intel Corporation
    Inventors: Ashok N. Kabadi, Frank R. DeWeese
  • Publication number: 20030168738
    Abstract: To decrease the thickness and bulk of an electronic assembly, the connectors of an integrated circuit (IC) package are releaseably coupled to corresponding receptors of an underlying substrate. In one embodiment, an IC package having ball-grid-array (BGA) connectors is mounted on a socketable substrate having mating receptors. The BGA balls are formed of gold-plated copper. The ball/receptor interface requires a minimum of vertical insertion or removal force and provides a gas-tight contact. Methods of fabrication, as well as application of the electronic assembly to a data processing system, are also described.
    Type: Application
    Filed: March 8, 2002
    Publication date: September 11, 2003
    Applicant: Intel Corporation
    Inventors: Ashok N. Kabadi, Harry L. Hampton
  • Patent number: 6529385
    Abstract: Apparatus and methods for connecting a device to an integrated circuit. The apparatus includes an insulating substrate that has two major sides and a number of sites for housing components. Each site has a first node on one of the two sides of the insulating substrate and a second node on the other of the two sides of the insulating substrate. Each site also has components that are aligned normal to the sides of the insulating substrate and are connected to the nodes at the site. Such apparatus are useful as adapters for testing an integrated circuit, such as connecting a test device to the integrated circuit with the adapter and observing and/or driving signals through the adapter.
    Type: Grant
    Filed: August 25, 1999
    Date of Patent: March 4, 2003
    Assignee: Intel Corporation
    Inventors: Gary W. Brady, Harry L. Hampton, III, Michael T. White, Ashok N. Kabadi
  • Patent number: 6269864
    Abstract: A heat sink for a microprocessor includes a thermally conductive base having a plurality of fin structures upwardly extending from the thermally conductive base. The plurality of fin structures having a first surface comprising a plurality of surface area enhancer structures to increase a convection surface area of the heat sink for a given volume of a heat sink to enhance heat dissipation from the heat sink.
    Type: Grant
    Filed: February 18, 2000
    Date of Patent: August 7, 2001
    Assignee: Intel Corporation
    Inventor: Ashok N. Kabadi
  • Patent number: 6097609
    Abstract: An electronic packaging assembly is disclosed. An electronic component is disposed on a socketing substrate utilizing a ball grid array or land grid array. The socketing substrate contains a series of pins that are embedded within the thickness of the socketing substrate. The pins correspond with the ball grid array or land grid array contacts of the electronic component. The socketing substrate is mounted onto a motherboard using an array of solder balls that correspond to and are disposed on, the end of the pins facing the motherboard. If desired, the electronic component may be protected by a metal lid. If desired, socketing substrates can be disposed on both sides of a motherboard.
    Type: Grant
    Filed: December 30, 1998
    Date of Patent: August 1, 2000
    Assignee: Intel Corporation
    Inventor: Ashok N. Kabadi
  • Patent number: 5057023
    Abstract: A connection system for use in connecting a high density flexible circuit directly to a surface mounted integrated circuit component mounted on a printed circuit board. The connection system utilizes an upper and lower stiffener plate to route the contacts of the high density flexible circuit to the pins of the integrated circuit component. The connection system utilizes silicone rubber pressure rods to create a force on the contacts of the higher density flexible circuit to ensure reliable connection to the leads of the surface mounted components. The connection system utilizes comb spacers which define slots to align the contacts of the high density circuit to the pins of the integrated circuit component and a top clamp to retain the assembly onto the integrated circuit component.
    Type: Grant
    Filed: June 1, 1990
    Date of Patent: October 15, 1991
    Assignee: Intel Corporation
    Inventors: Ashok N. Kabadi, Leonard O. Turner, Ronald C. Flamm
  • Patent number: 4917613
    Abstract: A connector system for coupling electrical cables with electrical apparatus such as integrated circuits and printed circuit boards. The present invention discloses a connector system for coupling electrical cables, preferably high density flexible circuits, with electrical apparatus. The connection system discloses a stiffener plate having a slot therein cut at a 45 degree angle from one corner of the stiffener plate to a second distal point of the stiffener plate. A pair of flexible circuits may be disposed in the stiffener plate and bent at 90 degree angles to the plate for coupling to a surface of the stiffener plate. The flexible circuits are of a design allowing for placement of electrical conductive pads along four edges of the stiffener plate, thus maximizing the density of electrical connections in the connection system.
    Type: Grant
    Filed: November 4, 1988
    Date of Patent: April 17, 1990
    Assignee: Intel Corporation
    Inventor: Ashok N. Kabadi
  • Patent number: 4850883
    Abstract: A clamping system for use in connecting high density flexible circuit to a rigid printed circuit board. The clamping system utilizes metal-on-elastomer (MOE) strips contained in a MOE holder and held in place by clamping components to provide electrical connections between the high density flexible circuit and the rigid printed circuit board. The clamping system utilizes a flexible mouth surrounding the high density flexible circuit to alleviate stress on the high density flexible circuit, a special plating on the conductors of the high density flexible circuit to prevent oxidation, and a stiffener clamp to provide stability for the MOE strips.
    Type: Grant
    Filed: May 21, 1987
    Date of Patent: July 25, 1989
    Assignee: Intel Corporation
    Inventor: Ashok N. Kabadi
  • Patent number: 4798918
    Abstract: A high density flexible circuit for coupling electrical devices. The flexible circuit has signal and ground traces on both sides of the flexible circuit. Each signal trace is surrounded by ground traces. There is a ground trace on either side of each signal trace and two ground traces located below each signal trace. This system of placing ground traces surrounding each signal trace reduces electrical noise between the signal traces and reduces the electrical capacitance of the circuit.
    Type: Grant
    Filed: September 21, 1987
    Date of Patent: January 17, 1989
    Assignee: Intel Corporation
    Inventors: Ashok N. Kabadi, Leonard O. Turner, Michael T. White