Patents by Inventor Ashok T. Ramu

Ashok T. Ramu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11336295
    Abstract: A system, a method and a computer program product for storing data, which include receiving a data stream having a plurality of transactions that include at least one portion of data, determining whether at least one portion of data within at least one transaction is substantially similar to at least another portion of data within at least one transaction, clustering together at least one portion of data and at least another portion of data within at least one transaction, selecting one of at least one portion of data and at least another portion of data as a representative of at least one portion of data and at least another portion of data in the received data stream, and storing each representative of a portion of data from each transaction in the plurality of transactions, wherein a plurality of representatives is configured to form a chain representing the received data stream.
    Type: Grant
    Filed: November 27, 2019
    Date of Patent: May 17, 2022
    Assignee: Exagrid Systems, Inc.
    Inventors: Mark Bennett Hecker, Ashok T. Ramu
  • Patent number: 10784382
    Abstract: A PIN diode has an anode spaced away from a central region of a top surface of a substrate, such that the anode is in a corner or at a side edge of the top surface. Alternatively, the PIN diode has an anode surrounded by a shield layer. The PIN diode reduces unwanted parasitic capacitance to increase the reverse isolation of RF switches and to reduce the diffusion capacitance to increase the f3dB frequency specification of amplifier circuits. The PIN diode dramatically reduces the values of both parasitic and diffusion capacitances, which enables its application in switches and amplifiers under a wide variety of bias conditions including reverse, low-moderate forward, and large forward-bias; which enables bonding to a much larger metal area than the active electrode, with negligible increase in the parasitic capacitance; and which enables reliable wire-bonding by presenting a highly planar metal surface.
    Type: Grant
    Filed: August 13, 2018
    Date of Patent: September 22, 2020
    Inventors: Ashok T. Ramu, Robert J. Bayruns, Michel Francois
  • Publication number: 20200099392
    Abstract: A system, a method and a computer program product for storing data, which include receiving a data stream having a plurality of transactions that include at least one portion of data, determining whether at least one portion of data within at least one transaction is substantially similar to at least another portion of data within at least one transaction, clustering together at least one portion of data and at least another portion of data within at least one transaction, selecting one of at least one portion of data and at least another portion of data as a representative of at least one portion of data and at least another portion of data in the received data stream, and storing each representative of a portion of data from each transaction in the plurality of transactions, wherein a plurality of representatives is configured to form a chain representing the received data stream.
    Type: Application
    Filed: November 27, 2019
    Publication date: March 26, 2020
    Inventors: Mark Bennett Hecker, Ashok T. Ramu
  • Patent number: 10566449
    Abstract: The present invention is a FET having a p-doped or acceptor-doped layer underneath a FET channel to enable E/D Mode operation. A FET threshold voltage is tunable through a voltage applied to the p-doped layer via a metal contact such as a threshold-control terminal (TCT). The present invention has a dual E/D mode operation of a single FET device, and also a dual E/D mode operation with a single-polarity positive power supply voltage. The FET of the present invention is fabricated to enable dual enhancement-mode/depletion-mode (E-Mode/D-Mode) high electron mobility transistors (HEMTs), to enable dual E/D Mode operation by incorporating a p-doped or acceptor doped region underneath the channel, to achieve a tunable threshold voltage by varying the bias voltage on a fourth terminal called the threshold-control terminal (TCT) that contacts the p-doped layer, and to enable Dual E/D-Mode operation of a HEMT with a single-polarity positive power supply voltage.
    Type: Grant
    Filed: April 20, 2018
    Date of Patent: February 18, 2020
    Assignee: Duet Microelectronics, Inc.
    Inventors: John Bayruns, Robert J. Bayruns, Ashok T. Ramu
  • Patent number: 10498356
    Abstract: A system, a method and a computer program product for storing data, which include receiving a data stream having a plurality of transactions that include at least one portion of data, determining whether at least one portion of data within at least one transaction is substantially similar to at least another portion of data within at least one transaction, clustering together at least one portion of data and at least another portion of data within at least one transaction, selecting one of at least one portion of data and at least another portion of data as a representative of at least one portion of data and at least another portion of data in the received data stream, and storing each representative of a portion of data from each transaction in the plurality of transactions, wherein a plurality of representatives is configured to form a chain representing the received data stream.
    Type: Grant
    Filed: October 13, 2011
    Date of Patent: December 3, 2019
    Assignee: Exagrid Systems, Inc.
    Inventors: Mark Bennett Hecker, Ashok T. Ramu
  • Publication number: 20190326425
    Abstract: The present invention is a FET having a p-doped or acceptor-doped layer underneath a FET channel to enable E/D Mode operation. A FET threshold voltage is tunable through a voltage applied to the p-doped layer via a metal contact such as a threshold-control terminal (TCT). The present invention has a dual E/D mode operation of a single FET device, and also a dual E/D mode operation with a single-polarity positive power supply voltage. The FET of the present invention is fabricated to enable dual enhancement-mode/depletion-mode (E-Mode/D-Mode) high electron mobility transistors (HEMTs), to enable dual E/D Mode operation by incorporating a p-doped or acceptor doped region underneath the channel, to achieve a tunable threshold voltage by varying the bias voltage on a fourth terminal called the threshold-control terminal (TCT) that contacts the p-doped layer, and to enable Dual E/D-Mode operation of a HEMT with a single-polarity positive power supply voltage.
    Type: Application
    Filed: April 20, 2018
    Publication date: October 24, 2019
    Applicant: DUET MICROELECTRONICS LLC
    Inventors: John Bayruns, Robert J. Bayruns, Ashok T. Ramu
  • Publication number: 20190267481
    Abstract: The present invention improves the linearity characteristics of a transistor, namely the input/output intercept points (IIP3/OIP3) and intermodulation distortion (IM3), while maintaining a high transconductance and high electron velocity in the conducting channel. The present invention also improves the manufacturability, yield, and immunity to bias-point drift, of a linear transistor. In one embodiment, the present invention implements triple pulse doping or even higher pulse doping for immunity to process variation as well as low parasitic leakage. In an alternative embodiment, the present invention implements a bilinear V-shaped composition grading for engineering the ID-VGS curve for high OIP3. In another alternative embodiment, the present invention implements a quadratic or U-shaped composition grading for engineering the ID-VGS curve for high OIP3.
    Type: Application
    Filed: February 26, 2018
    Publication date: August 29, 2019
    Inventors: Ashok T. Ramu, Robert Bayruns
  • Publication number: 20190267480
    Abstract: A field effect transistor (FET) includes a substrate, a back barrier disposed on the substrate, a channel disposed on the back barrier, a front barrier disposed on the channel, a source, and a drain, such that at least one of the front barrier and the back barrier includes an anti-barrier-conduction (ABC) spacer which reduces parasitic conduction on a path from the source to the drain through at least one of the front barrier and the back barrier, reduces ON-state leakage from the channel to gate or substrate of the FET via resonant tunneling, and reduces OFF-state leakage by presenting tall barriers to electrons as well as electron-holes. This results in a highly linear, low gate leakage, low parasitic conduction, and low noise operation of FET.
    Type: Application
    Filed: January 4, 2019
    Publication date: August 29, 2019
    Applicant: DUET MICROELECTRONICS INC.
    Inventors: Ashok T. Ramu, Keun-Yong Ban
  • Patent number: 10347738
    Abstract: Fabrication of a dual enhancement-mode/depletion-mode (E-Mode/D-Mode) high electron mobility transistor (HEMT) called a threshold control terminal HEMT (TCT-HEMT) is performed which reduces capacitance between the TCT electrode and the source and drain electrodes of a TCT-HEMT, since such a capacitance may be parasitic, and which fabricates a TCT-HEMT capable of high-frequency operation. A method for fabricating a field-effect transistor (FET) includes: providing a substrate; disposing a back barrier on the substrate to form a base stack; forming a doped layer on the base stack; grow additional layers, including a threshold-control terminal (TCT) access layer; etch a pattern in at least one of the doped layer and the additional layers; and disposing a TCT contact on the TCT access layer.
    Type: Grant
    Filed: May 15, 2018
    Date of Patent: July 9, 2019
    Assignee: Duet Microelectronics, Inc.
    Inventors: Ashok T. Ramu, Keun-Yong Ban, John Bayruns, Robert J. Bayruns
  • Publication number: 20190109242
    Abstract: A PIN diode has an anode spaced away from a central region of a top surface of a substrate, such that the anode is in a corner or at a side edge of the top surface. Alternatively, the PIN diode has an anode surrounded by a shield layer. The PIN diode reduces unwanted parasitic capacitance to increase the reverse isolation of RF switches and to reduce the diffusion capacitance to increase the f3dB frequency specification of amplifier circuits. The PIN diode dramatically reduces the values of both parasitic and diffusion capacitances, which enables its application in switches and amplifiers under a wide variety of bias conditions including reverse, low-moderate forward, and large forward-bias; which enables bonding to a much larger metal area than the active electrode, with negligible increase in the parasitic capacitance; and which enables reliable wire-bonding by presenting a highly planar metal surface.
    Type: Application
    Filed: August 13, 2018
    Publication date: April 11, 2019
    Applicant: DUET MICROELECTRONICS INC.
    Inventors: Ashok T. Ramu, Robert J. Bayruns, Michel Francois
  • Patent number: 10114831
    Abstract: A system, a method, and a computer program product for delta version clustering and re-anchoring are provided. A first anchor having a plurality of delta-compressed versions of data dependent on the first anchor is generated. The first anchor and the plurality of delta-compressed versions form a cluster. A second anchor is generated. The first anchor is replaced with the second anchor. The replacing includes re-computing at least one delta-compressed version in the plurality of delta-compressed versions to be dependent on the second anchor. The second anchor replaces the first anchor as an anchor of the cluster.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: October 30, 2018
    Assignee: Exagrid Systems, Inc.
    Inventors: Adrian VanderSpek, Jamey C. Poirier, Lucas H. Makosky, Ashok T. Ramu, Mark Bennett Hecker, Thomas G. Hansen, David G. Therrien
  • Publication number: 20140052700
    Abstract: A system, a method, and a computer program product for delta version clustering and re-anchoring are provided. A first anchor having a plurality of delta-compressed versions of data dependent on the first anchor is generated. The first anchor and the plurality of delta-compressed versions form a cluster. A second anchor is generated. The first anchor is replaced with the second anchor. The replacing includes re-computing at least one delta-compressed version in the plurality of delta-compressed versions to be dependent on the second anchor. The second anchor replaces the first anchor as an anchor of the cluster.
    Type: Application
    Filed: August 7, 2013
    Publication date: February 20, 2014
    Applicant: Exagrid Systems, Inc.
    Inventors: Adrian VanderSpek, Jamey C. Poirier, Lucas H. Makosky, Ashok T. Ramu, Mark Bennett Hecker, Thomas G. Hansen, David G. Therrien
  • Publication number: 20130066868
    Abstract: A system, a method and a computer program product for storing data, which include receiving a data stream having a plurality of transactions that include at least one portion of data, determining whether at least one portion of data within at least one transaction is substantially similar to at least another portion of data within at least one transaction, clustering together at least one portion of data and at least another portion of data within at least one transaction, selecting one of at least one portion of data and at least another portion of data as a representative of at least one portion of data and at least another portion of data in the received data stream, and storing each representative of a portion of data from each transaction in the plurality of transactions, wherein a plurality of representatives is configured to form a chain representing the received data stream.
    Type: Application
    Filed: October 13, 2011
    Publication date: March 14, 2013
    Applicant: EXAGRID SYSTEMS, INC.
    Inventors: Mark Bennett Hecker, Ashok T. Ramu
  • Patent number: 7925623
    Abstract: Embodiments of this invention provide primary magnetic disk data storage capacity to clients while at the same time making sure that client data is replicated locally and at an offsite location to protect from all forms of data loss.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: April 12, 2011
    Assignee: Exagrid Systems, Inc.
    Inventors: David G. Therrien, James E. Pownell, Herman Robert Kenna, Adrian VanderSpek, Thomas G. Hansen, Ashok T. Ramu, Cory Lee Sawyer
  • Patent number: 7246275
    Abstract: The present invention relates to a computer primary data storage system that integrates the functionality of file backup and remote replication to provide an integrated storage system that protects its data from loss related to system or network failures or the physical loss of a data center.
    Type: Grant
    Filed: September 10, 2003
    Date of Patent: July 17, 2007
    Assignee: Exagrid Systems, Inc.
    Inventors: David G. Therrien, James E. Pownell, Adrian VanderSpek, Herman Robert Kenna, Ashok T. Ramu, Maxwell Joel Berenson
  • Publication number: 20040093555
    Abstract: The present invention relates to a computer primary data storage system that integrates the functionality of file backup and remote replication to provide an integrated storage system that protects its data from loss related to system or network failures or the physical loss of a data center.
    Type: Application
    Filed: September 10, 2003
    Publication date: May 13, 2004
    Inventors: David G. Therrien, James E. Pownell, Adrian VanderSpek, Herman Robert Kenna, Ashok T. Ramu, Maxwell Joel Berenson
  • Publication number: 20040088331
    Abstract: Embodiments of this invention provide primary magnetic disk data storage capacity to clients while at the same time making sure that client data is replicated locally and at an offsite location to protect from all forms of data loss.
    Type: Application
    Filed: September 10, 2003
    Publication date: May 6, 2004
    Inventors: David G. Therrien, James E. Pownell, Herman Robert Kenna, Adrian VanderSpek, Thomas G. Hansen, Ashok T. Ramu, Cory Lee Sawyer