Abstract: A method of computing the product D of two finite field elements B and C modulo an irreducible polynomial f.sub.1 (x), wherein the finite field elements B and C are represented in terms of an optimal normal basis (ONB) of Type 1 over a field F.sub.2.spsb.n and the irreducible polynomial f.sub.1 (x) being of degree n, which comprises the steps of representing the element B as a vector of binary digits b.sub.i, where b.sub.i is a co-efficient of an i.sup.th basis element of the ONB representation of element B, in polynomial order, representing the element C as a vector of binary digits c.sub.i, where c.sub.i is a co-efficient of an i.sup.th basis element of the ONB representation of element C, arranged in polynomial order, initializing a register A, selecting a digit c.sub.i of the vector C, computing a partial product vector A of the i.sup.th digit c.sub.i of the element C and the vector B, adding the partial product to the register A, shifting the register A, reducing the partial product A by a multiple f.

Abstract: A finite field inverse circuit has a finite field data unit (1112) and an inverse control unit (1110). The inverse control unit includes (1110) a k.sub.l and k.sub.u decrementer pair (1108, 1122), a k.sub.l -k.sub.u difference unit (1106), an inverse control finite state machine (1102), and a one-bit memory (1104) coupled to the inverse control finite state machine (1102). The finite field data unit (1112) includes four m bit wide registers that are shift registers designated as B (1120), A (1118), M (1114), and C (1116), where B- is a first register, A- is a second register, M- is a irreducible polynomial register, and C- is a field element register. An the irreducible polynomial is loaded left justified in the M-register, a field element to be inverted is loaded left justified in the C-register, and a single "1" is loaded in an LSB bit of the B-register. The field element is then inverted in 2n+2 system clock cycles where n is a field size associated with the field element.