Patents by Inventor Ashraf ElSharif
Ashraf ElSharif has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11880304Abstract: To facilitate an efficient processing of contended cache lines, a cache controller that is associated with a requestor receives a fetch request for data from the requestor. The fetch request is associated with a cache scope designation. If the data is in a high-level cache (e.g., L1 cache) associated with the requestor, the cache controller returns the requested data to the requestor. If the data is not in the high-level cache or if the data is not within the cache pool identified by the cache scope of search designation, and/or if obtaining the data is contentious, the controller returns a cache miss, undeliverable data, and request done instruction to the requestor. Such scheme allows or permits address contention events when the requestor deems such events are necessary and/or when important. As such, address contention events, performance, latencies, increased executions times, inefficient use of resources, may be diminished.Type: GrantFiled: May 24, 2022Date of Patent: January 23, 2024Assignee: International Business Machines CorporationInventors: Taylor J Pritchard, Aaron Tsai, Richard Joseph Branciforte, Ashraf ElSharif, Gregory William Alexander, Deanna Postles Dunn Berger, Michael Fee
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Publication number: 20230385195Abstract: To facilitate an efficient processing of contended cache lines, a cache controller that is associated with a requestor receives a fetch request for data from the requestor. The fetch request is associated with a cache scope designation. If the data is in a high-level cache (e.g., L1 cache) associated with the requestor, the cache controller returns the requested data to the requestor. If the data is not in the high-level cache or if the data is not within the cache pool identified by the cache scope of search designation, and/or if obtaining the data is contentious, the controller returns a cache miss, undeliverable data, and request done instruction to the requestor. Such scheme allows or permits address contention events when the requestor deems such events are necessary and/or when important. As such, address contention events, performance, latencies, increased executions times, inefficient use of resources, may be diminished.Type: ApplicationFiled: May 24, 2022Publication date: November 30, 2023Inventors: Taylor J. Pritchard, Aaron Tsai, Richard Joseph Branciforte, Ashraf ElSharif, Gregory William Alexander, Deanna Postles Dunn Berger, Michael Fee
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Publication number: 20230315633Abstract: A computer system includes a processor core and a memory system in signal communication with the processor core. The memory system includes a first cache and a second cache. The first cache is arranged at a first level of a hierarchy in the memory system and is configured to store a plurality of first-cache entries. The second cache is arranged at a second level of the hierarchy that is lower than the first level, and stores a plurality of second-cache entries. The first cache maintains a directory that contains information for each of the first-cache entries. The second cache maintains a shadow pointer directory (SPD) that includes one or more SPD entries that maps each of the first-cache entries to a corresponding second cache entry at a lower-level cache location.Type: ApplicationFiled: April 4, 2022Publication date: October 5, 2023Inventors: Ashraf ElSharif, Richard Joseph Branciforte, Gregory William Alexander, Deanna Postles Dunn Berger, Timothy Bronson, Aaron Tsai, Taylor J. Pritchard, Markus Kaltenbach, Christian Jacobi, Michael A. Blake
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Patent number: 10956637Abstract: According to one or more embodiments, a method for adding parity protection for any uncovered latches of a circuit design is provided. The method includes determining latches that are not covered by current parity protection of the circuit design to output a list of the uncovered latches. The method includes executing a clustering operation that iteratively generates latch groupings according to physical design information and clock gating domains, and that outputs an updated design incorporating the latch groupings. Note that each latch grouping generates a corresponding parity bit to provide the parity protection to minimize adverse impacts on timing, routing, and power consumption of the circuit design. The method also includes adding the updated design with the parity protection to the circuit design to generate a final hardware design.Type: GrantFiled: May 7, 2019Date of Patent: March 23, 2021Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ashraf ElSharif, Kenneth Douglas Klapproth, Jason D. Kohl
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Patent number: 10489292Abstract: Embodiments of the present invention are directed to a computer-implemented method for ownership tracking updates across multiple simultaneous operations. A non-limiting example of the computer-implemented method includes receiving, by a cache directory control circuit, a message to update a cache directory entry. The method further includes, in response, updating, by the cache directory control circuit, the cache directory entry, and generating a reverse compare signal including an updated ownership vector of a memory line corresponding to the cache directory entry. The method further includes sending the reverse compare signal to a cache controller associated with the cache directory entry.Type: GrantFiled: November 20, 2017Date of Patent: November 26, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael A. Blake, Timothy C. Bronson, Ashraf ElSharif, Kenneth D. Klapproth, Vesselina K. Papazova, Guy G. Tracy
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Patent number: 10482015Abstract: Embodiments of the present invention are directed to a computer-implemented method for ownership tracking updates across multiple simultaneous operations. A non-limiting example of the computer-implemented method includes receiving, by a cache directory control circuit, a message to update a cache directory entry. The method further includes, in response, updating, by the cache directory control circuit, the cache directory entry, and generating a reverse compare signal including an updated ownership vector of a memory line corresponding to the cache directory entry. The method further includes sending the reverse compare signal to a cache controller associated with the cache directory entry.Type: GrantFiled: May 18, 2017Date of Patent: November 19, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael A. Blake, Timothy C. Bronson, Ashraf ElSharif, Kenneth D. Klapproth, Vesselina K. Papazova, Guy G. Tracy
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Publication number: 20190266305Abstract: According to one or more embodiments, a method for adding parity protection for any uncovered latches of a circuit design is provided. The method includes determining latches that are not covered by current parity protection of the circuit design to output a list of the uncovered latches. The method includes executing a clustering operation that iteratively generates latch groupings according to physical design information and clock gating domains, and that outputs an updated design incorporating the latch groupings. Note that each latch grouping generates a corresponding parity bit to provide the parity protection to minimize adverse impacts on timing, routing, and power consumption of the circuit design. The method also includes adding the updated design with the parity protection to the circuit design to generate a final hardware design.Type: ApplicationFiled: May 7, 2019Publication date: August 29, 2019Inventors: Ashraf ElSharif, Kenneth Douglas Klapproth, Jason D. Kohl
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Patent number: 10379776Abstract: An aspect includes interlocking operations in an address-sliced cache system. A computer-implemented method includes determining whether a dynamic memory relocation operation is in process in the address-sliced cache system. Based on determining that the dynamic memory relocation operation is in process, a key operation is serialized to maintain a sequenced order of completion of the key operation across a plurality of slices and pipes in the address-sliced cache system. Based on determining that the dynamic memory relocation operation is not in process, a plurality of key operation requests is allowed to launch across two or more of the slices and pipes in parallel in the address-sliced cache system while ensuring that only one instance of the key operations is in process across all of the slices and pipes at a same time.Type: GrantFiled: May 24, 2017Date of Patent: August 13, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Deanna P. Berger, Michael A. Blake, Ashraf Elsharif, Kenneth D. Klapproth, Pak-kin Mak, Robert J. Sonnelitter, III, Guy G. Tracy
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Patent number: 10325049Abstract: According to one or more embodiments, a method for adding parity protection for any uncovered latches of a circuit design is provided. The method includes determining latches that are not covered by current parity protection of the circuit design to output a list of the uncovered latches. The method includes executing a clustering operation that iteratively generates latch groupings according to physical design information and clock gating domains, and that outputs an updated design incorporating the latch groupings. Note that each latch grouping generates a corresponding parity bit to provide the parity protection to minimize adverse impacts on timing, routing, and power consumption of the circuit design. The method also includes adding the updated design with the parity protection to the circuit design to generate a final hardware design.Type: GrantFiled: January 18, 2017Date of Patent: June 18, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Ashraf ElSharif, Kenneth Douglas Klapproth, Jason D. Kohl
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Publication number: 20180341422Abstract: An aspect includes interlocking operations in an address-sliced cache system. A computer-implemented method includes determining whether a dynamic memory relocation operation is in process in the address-sliced cache system. Based on determining that the dynamic memory relocation operation is in process, a key operation is serialized to maintain a sequenced order of completion of the key operation across a plurality of slices and pipes in the address-sliced cache system. Based on determining that the dynamic memory relocation operation is not in process, a plurality of key operation requests is allowed to launch across two or more of the slices and pipes in parallel in the address-sliced cache system while ensuring that only one instance of the key operations is in process across all of the slices and pipes at a same time.Type: ApplicationFiled: May 24, 2017Publication date: November 29, 2018Inventors: Deanna P. Berger, Michael A. Blake, Ashraf Elsharif, Kenneth D. Klapproth, Pak-kin Mak, Robert J. Sonnelitter, III, Guy G. Tracy
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Publication number: 20180336135Abstract: Embodiments of the present invention are directed to a computer-implemented method for ownership tracking updates across multiple simultaneous operations. A non-limiting example of the computer-implemented method includes receiving, by a cache directory control circuit, a message to update a cache directory entry. The method further includes, in response, updating, by the cache directory control circuit, the cache directory entry, and generating a reverse compare signal including an updated ownership vector of a memory line corresponding to the cache directory entry. The method further includes sending the reverse compare signal to a cache controller associated with the cache directory entry.Type: ApplicationFiled: November 20, 2017Publication date: November 22, 2018Inventors: Michael A. Blake, Timothy C. Bronson, Ashraf ElSharif, Kenneth D. Klapproth, Vesselina K. Papazova, Guy G. Tracy
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Publication number: 20180336134Abstract: Embodiments of the present invention are directed to a computer-implemented method for ownership tracking updates across multiple simultaneous operations. A non-limiting example of the computer-implemented method includes receiving, by a cache directory control circuit, a message to update a cache directory entry. The method further includes, in response, updating, by the cache directory control circuit, the cache directory entry, and generating a reverse compare signal including an updated ownership vector of a memory line corresponding to the cache directory entry. The method further includes sending the reverse compare signal to a cache controller associated with the cache directory entry.Type: ApplicationFiled: May 18, 2017Publication date: November 22, 2018Inventors: Michael A. Blake, Timothy C. Bronson, Ashraf ElSharif, Kenneth D. Klapproth, Vesselina K. Papazova, Guy G. Tracy
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Publication number: 20180203968Abstract: According to one or more embodiments, a method for adding parity protection for any uncovered latches of a circuit design is provided. The method includes determining latches that are not covered by current parity protection of the circuit design to output a list of the uncovered latches. The method includes executing a clustering operation that iteratively generates latch groupings according to physical design information and clock gating domains, and that outputs an updated design incorporating the latch groupings. Note that each latch grouping generates a corresponding parity bit to provide the parity protection to minimize adverse impacts on timing, routing, and power consumption of the circuit design. The method also includes adding the updated design with the parity protection to the circuit design to generate a final hardware design.Type: ApplicationFiled: January 18, 2017Publication date: July 19, 2018Inventors: Ashraf ElSharif, Kenneth Douglas Klapproth, Jason D. Kohl