Abstract: A circuit includes a receiver having first and second differential input pairs and one differential output pair, the receiver outputting the first differential inputs at the differential outputs in a first mode and applying test signals to the second differential inputs and outputting the second differential inputs at the differential outputs in a second mode; and switches coupled to the first and second differential inputs to disconnect the test input signals from the second differential inputs during the first mode and to disable the receiver input signals by connecting first differential inputs to local core voltage while tri-stating the transmitter on the other side of the link during the second mode.

Abstract: A circuit includes a receiver having first and second differential input pairs and one differential output pair, the receiver outputting the first differential inputs at the differential outputs in a first mode and applying test signals to the second differential inputs and outputting the second differential inputs at the differential outputs in a second mode; and switches coupled to the first and second differential inputs to disconnect the test input signals from the second differential inputs during the first mode and to disable the receiver input signals by connecting first differential inputs to local core voltage while tri-stating the transmitter on the other side of the link during the second mode.

Abstract: A circuit includes a receiver having first and second differential input pairs and one differential output pair, the receiver outputting the first differential inputs at the differential outputs in a first mode and applying test signals to the second differential inputs and outputting the second differential inputs at the differential outputs in a second mode; and switches coupled to the first and second differential inputs to disconnect the test input signals from the second differential inputs during the first mode and to disable the receiver input signals by connecting first differential inputs to local core voltage while tri-stating the transmitter on the other side of the link during the second mode.

Abstract: A circuit includes a receiver having first and second differential input pairs and one differential output pair, the receiver outputting the first differential inputs at the differential outputs in a first mode and applying test signals to the second differential inputs and outputting the second differential inputs at the differential outputs in a second mode; and switches coupled to the first and second differential inputs to disconnect the test input signals from the second differential inputs during the first mode and to disable the receiver input signals by connecting first differential inputs to local core voltage while tri-stating the transmitter on the other side of the link during the second mode.

Abstract: A phase-locked loop with training capability that reduces the time for clock recovery of a clock signal at a known frequency embedded in a data signal. Prior to the data signal being available, the phase-locked loop, in a training mode, acquires frequency and phase lock with a local oscillator signal. As a result, the output of the PLL is frequency locked substantially at the frequency of the clock embedded in the expected data signal. To achieve this result, in the training mode, the PLL compares the local oscillator signal divided by a first divider with the output clock signal divided by a second divider. Then the frequency of the output clock signal of the PLL equals the frequency of the local oscillator multiplied by the ratio of the divisor of the second divider over the divisor of the first divider. When the data signal is available, the PLL operates in a data receiving mode.

Abstract: A phase-locked loop with training capability that reduces the time for clock recovery of a clock signal at a known frequency embedded in a data signal. Prior to the data signal being available, the phase-locked loop, in a training mode, acquires frequency and phase lock with a local oscillator signal. As a result, the output of the PLL is frequency locked substantially at the frequency of the clock embedded in the expected data signal. To achieve this result, in the training mode, the PLL compares the local oscillator signal divided by a first divider with the output clock signal divided by a second divider. Then the frequency of the output clock signal of the PLL equals the frequency of the local oscillator multiplied by the ratio of the divisor of the second divider over the divisor of the first divider. When the data signal is available, the PLL operates in a data receiving mode.

Abstract: The invention provides a hybrid phase-locked loop (PLL) containing digital and analog portions for digital and analog adjustments, respectively, of an output signal. The hybrid PLL is simple in design. Off-the-shelf controlled oscillators, such as a current controlled oscillator (CCO) can be used with this hybrid PLL. The digital and the analog portions of the hybrid PLL are separate from the controlled oscillator. The digital portion is for a first adjustment of the frequency of the output signal, such as during a calibration. The analog portion is for fine phase and frequency adjustment of the output signal.

Abstract: A system clock signal is distributed to a plurality of load devices via a plurality of phase correction circuits each coupled to a different pair of a plurality of pairs of clock signal conductors. The proximal end of one of the pair of conductors is coupled to the output of a delay line and receives a phase corrected version of the system clock signal. The distal end of this conductor is coupled to the load device at a clock connection node. The clock connection node is fed back to the phase correction circuit via the other one of the pair of conductors. The first and second conductors have equal path lengths in order to provide equal propagation delays. The clock signal fed back from the load device node is coupled as a feedback input to a three input phase detector circuit. The other two inputs are the clock signal output from the phase correction circuit delay line and the system clock signal.

Abstract: A system clock signal is delivered to a plurality of load devices by means of a common loop filter and delay line and a plurality of phase detectors and charge pumps each associated to a different load. The delay line provides a plurality of substantially identical phase corrected clock signals, each clock signal being coupled to the associated load device via an associated conductor member. In one embodiment, each conductor member comprises a loop consisting of a pair of conductors having substantially identical path lengths. The phase adjusted clock signals on the proximal end of the outbound conductor are coupled back as a first feedback signal to one input of the associated phase detector. Another feedback signal comprises the clock signal returned from the device node along the second conductor of the pair. A third input to the phase detector is the system input clock signal, which is also coupled to a reference input of the delay line.

Abstract: A phase locked loop circuit (16) includes means to eliminate harmonic frequency locking. The phase locked loop includes a voltage controlled oscillator (1) which provides an output signal (V.sub.out) which is compared with the input signal (V.sub.in) by a phase detector (4). The output signal from the phase detector is integrated and the output signal of the integrator (7) is placed on the control input lead of the voltage controlled oscillator. The output signal of the voltage controlled oscillator is provided to a frequency detector (14, 17) which determines if the output frequency is within a predefined range. If the output frequency is above the predetermined range, a limiter circuit (15) provides a low voltage output signal to the control input lead of the VCO in order to pull the input voltage of the VCO to a voltage which corresponds with the appropriate operating range of the phase locked loop.