Abstract: A remote enclosure houses multiple subsystems. A first subsystem is coupled to a central office over a high-speed communication channel such as an OC-3 channel. The first subsystem extracts a downstream message from a first embedded operations channel included in the high-speed communication channel. The first subsystem also, when the downstream message is targeted to a first unit included in the first subsystem, forwards the message to a unit that processes the message for the first unit. When the message is not targeted to any unit included in the first subsystem, the first subsystem forwards the downstream message to another subsystem housed within the remote enclosure via a second embedded operations channel included in a second communication channel. The second subsystem is subtended from the first subsystem and is connected thereto by the second communication channel.

Abstract: A remote enclosure houses multiple subsystems. A first subsystem is coupled to a central office over a high-speed communication channel such as an OC-3 channel. The first subsystem extracts a downstream message from a first embedded operations channel included in the high-speed communication channel. The first subsystem also, when the downstream message is targeted to a first unit included in the first subsystem, forwards the message to a unit that processes the message for the first unit. When the message is not targeted to any unit included in the first subsystem, the first subsystem forwards the downstream message to another subsystem housed within the remote enclosure via a second embedded operations channel included in a second communication channel. The second subsystem is subtended from the first subsystem and is connected thereto by the second communication channel.

Abstract: A computer system includes a parity bit emulator circuit which generates a parity bit to be associated with a data byte output by a signal in-line memory module (SIMM) to a CPU. Each parity bit emulator monitors four consecutive write cycles to determine whether the system parity is even or odd, and thereafter monitors each write cycle to determine if a data transfer error has occurred during a write from the CPU to the SIMM. A state machine circuit provides appropriate timing for write and read cycle memory access protocols.