Patents by Inventor Ashutosh Garg

Ashutosh Garg has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210191724
    Abstract: Embodiments described herein provide for an instruction and associated logic to enable a vector multiply add instructions with automatic zero skipping for sparse input. One embodiment provides for a general-purpose graphics processor comprising logic to perform operations comprising fetching a hardware macro instruction having a predicate mask, a repeat count, and a set of initial operands, where the initial operands include a destination operand and multiple source operands. The hardware macro instruction is configured to perform one or more multiply/add operations on input data associated with a set of matrices.
    Type: Application
    Filed: December 23, 2019
    Publication date: June 24, 2021
    Applicant: Intel Corporation
    Inventors: Supratim Pal, Sasikanth Avancha, Ishwar Bhati, Wei-Yu Chen, Dipankar Das, Ashutosh Garg, Chandra S. Gurram, Junjie Gu, Guei-Yuan Lueh, Subramaniam Maiyuran, Jorge E. Parra, Sudarshan Srinivasan, Varghese George
  • Patent number: 11042370
    Abstract: Embodiments described herein provided for an instruction and associated logic to enable GPGPU program code to access special purpose hardware logic to accelerate dot product operations. One embodiment provides for a graphics processing unit comprising a fetch unit to fetch an instruction for execution and a decode unit to decode the instruction into a decoded instruction. The decoded instruction is a matrix instruction to cause the graphics processing unit to perform a parallel dot product operation. The GPGPU also includes a systolic dot product unit to execute the decoded instruction across one or more SIMD lanes using multiple systolic layers, wherein to execute the decoded instruction, a dot product computed at a first systolic layer is to be output to a second systolic layer, wherein each systolic layer includes one or more sets of interconnected multipliers and adders, each set of multipliers and adders to generate a dot product.
    Type: Grant
    Filed: April 19, 2018
    Date of Patent: June 22, 2021
    Assignee: Intel Corporation
    Inventors: Subramaniam Maiyuran, Guei-Yuan Lueh, Supratim Pal, Ashutosh Garg, Chandra S. Gurram, Jorge E. Parra, Junjie Gu, Konrad Trifunovic, Hong Bin Liao, Mike B. Macpherson, Shubh B. Shah, Shubra Marwaha, Stephen Junkins, Timothy R. Bauer, Varghese George, Weiyu Chen
  • Patent number: 11030583
    Abstract: The present disclosure describes a system, method, and computer program for removing or replacing information in candidate profiles that may influence bias. The system identifies data in candidate profiles that may influence bias with respect to one or more defined classes of bias, such as gender, race, or age. The identified data is removed or replaced with an abstracted/neutral form of the data. The system may also remove information that personally identifies a candidate. In certain embodiments, the system determines what data is relevant for the job for which a candidate is applying and, for data that is relevant, at what level it is relevant (i.e., at the base value or an abstracted level). In such embodiments, the system removes data from the candidate's profile that is not relevant for the job role and, where applicable, abstracts some of the remaining data to levels that are relevant for the job role.
    Type: Grant
    Filed: December 4, 2018
    Date of Patent: June 8, 2021
    Assignee: Eightfold AI Inc.
    Inventors: Ashutosh Garg, Varun Kacholia
  • Patent number: 11030404
    Abstract: An intelligent system and method for analyzing documents and suggesting corrections based on diversity criteria include a processing device to analyze a job document, using a machine learning model, to identify a first expression representing a first qualification requirement favorable to a first class of applicants than a second class of applicants according to a diversity metric, responsive to identifying the first expression, determine, using a semantic relation map, a second expression representing a second qualification requirement that is less favorable to the first class of applicants when compared to the first expression, and responsive to determining that the second expression, present the second expression on the interface device as a suggested replacement to the first expression in the job document.
    Type: Grant
    Filed: September 25, 2020
    Date of Patent: June 8, 2021
    Assignee: Eightfold AI Inc.
    Inventors: Ashutosh Garg, Varun Kacholia, Ruoyu Roy Wang
  • Patent number: 11017426
    Abstract: Techniques for performing content performance analytics are disclosed in accordance with some embodiments. In some embodiments, a process for performing content performance analytics includes receiving content on a web site; performing content performance analytics of content available on the web site using a processor; generating a report that includes a recommended action based on the content performance analytics for the content on the web site; and automatically performing a recommended action based on the content performance analytics for the content on the web site.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: May 25, 2021
    Assignee: BloomReach Inc.
    Inventors: Ashutosh Garg, Vache Moroyan, Gagandeep Singh, Renuka Khandelwal, Praveen K. Patnala, William Uppington, Siddharth Balwani, Maksim Zanko
  • Publication number: 20210141857
    Abstract: An apparatus to facilitate matrix multiplication operations. The apparatus comprises multiplication hardware to operate in a dot product mode, wherein a multiplication stage included in the multiplication hardware is configured as a dot product of a number of bit vectors (N) to perform N×N multiplication operations on a plurality of multiplicands and perform addition operations on results of the N×N multiplication operations.
    Type: Application
    Filed: November 13, 2019
    Publication date: May 13, 2021
    Applicant: Intel Corporation
    Inventors: Nevin Mathew, Shubra Marwaha, Ashutosh Garg
  • Publication number: 20210125151
    Abstract: A system and method for event management including a processing device to identify target participants from the event participants, and transmit a request for information to each of the target participants, generate a corresponding first enriched talent profile associated with the at least one target participant, implement a machine learning module that is trained based on historical recruiting data relating to at least one of a talent event or an organization to which the at least one target participant belongs, for a calibrated position profile, execute the trained machine learning module using the first enriched talent profiles and the calibrated position profile as inputs to calculate a match score associated with each of first enriched talent profiles, and determine, based on calculated match scores, one or more target participants invited to meet at the talent event.
    Type: Application
    Filed: October 28, 2020
    Publication date: April 29, 2021
    Applicant: Eightfold AI Inc.
    Inventors: Yuet Ping Poon, Varun Kacholia, Ashutosh Garg, Anthony Hahn
  • Publication number: 20210103550
    Abstract: Embodiments described herein include software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. One embodiment provides for data aware sparsity via compressed bitstreams. One embodiment provides for block sparse dot product instructions. One embodiment provides for a depth-wise adapter for a systolic array.
    Type: Application
    Filed: December 15, 2020
    Publication date: April 8, 2021
    Applicant: Intel Corporation
    Inventors: Abhishek Appu, Subramaniam Maiyuran, Mike Macpherson, Fangwen Fu, Jiasheng Chen, Varghese George, Vasanth Ranganathan, Ashutosh Garg, Joydeep Ray
  • Publication number: 20210089301
    Abstract: Embodiments described herein provide an apparatus comprising a plurality of processing resources including a first processing resource and a second processing resource, a shared local memory communicatively coupled to the first processing resource and the second processing resource, and a processor to receive an instruction to initiate a matrix multiplication operation, write a first set of matrix data into a first set of registers, and share the first set of matrix data between the first processing resource and the second processing resource for use in the matrix multiplication operation. Other embodiments may be described and claimed.
    Type: Application
    Filed: September 25, 2019
    Publication date: March 25, 2021
    Applicant: Intel Corporation
    Inventors: SUBRAMANIAM MAIYURAN, VARGHESE GEORGE, JOYDEEP RAY, ASHUTOSH GARG, JORGE PARRA, SHUBH SHAH, SHUBRA MARWAHA
  • Publication number: 20210081603
    Abstract: A system and method for transferring annotations associated with a media file. An annotation associated with a media file is indexed to a first instance of that media file. By comparing features of the two instances, a mapping is created between the first instance of the media file and a second instance of the media file. The annotation can be indexed to the second instance using the mapping between the first and second instances. The annotation can be processed (displayed, stored, or modified) based on the index to the second instance.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Inventors: Mayur Datar, Ashutosh Garg, Vibhu Mittal
  • Publication number: 20210081201
    Abstract: An apparatus to facilitate utilizing structured sparsity in systolic arrays is disclosed. The apparatus includes a processor comprising a systolic array to receive data from a plurality of source registers, the data comprising unpacked source data, structured source data that is packed based on sparsity, and metadata corresponding to the structured source data; identify portions of the unpacked source data to multiply with the structured source data, the portions of the unpacked source data identified based on the metadata; and output, to a destination register, a result of multiplication of the portions of the unpacked source data and the structured source data.
    Type: Application
    Filed: November 30, 2020
    Publication date: March 18, 2021
    Applicant: Intel Corporation
    Inventors: Subramaniam Maiyuran, Jorge Parra, Ashutosh Garg, Chandra Gurram, Chunhui Mei, Durgesh Borkar, Shubra Marwaha, Supratim Pal, Varghese George, Wei Xiong, Yan Li, Yongsheng Liu, Dipankar Das, Sasikanth Avancha, Dharma Teja Vooturi, Naveen K. Mellempudi
  • Publication number: 20210073318
    Abstract: An apparatus to facilitate acceleration of matrix multiplication operations. The apparatus comprises a systolic array including matrix multiplication hardware to perform multiply-add operations on received matrix data comprising data from a plurality of input matrices and sparse matrix acceleration hardware to detect zero values in the matrix data and perform one or more optimizations on the matrix data to reduce multiply-add operations to be performed by the matrix multiplication hardware.
    Type: Application
    Filed: September 5, 2019
    Publication date: March 11, 2021
    Applicant: Intel Corporation
    Inventors: SUBRAMANIAM MAIYURAN, MATHEW NEVIN, JORGE PARRA, ASHUTOSH GARG, SHUBRA MARWAHA, SHUBH SHAH
  • Publication number: 20210035258
    Abstract: Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to skip computational operations for zero filled matrices and sub-matrices. Embodiments additionally provide techniques to maintain data compression through to a processing unit. Embodiments additionally provide an architecture for a sparse aware logic unit.
    Type: Application
    Filed: October 6, 2020
    Publication date: February 4, 2021
    Applicant: Intel Corporation
    Inventors: Joydeep Ray, Scott Janus, Varghese George, Subramaniam Maiyuran, Altug Koker, Abhishek Appu, Prasoonkumar Surti, Vasanth Ranganathan, Andrei Valentin, Ashutosh Garg, Yoav Harel, Arthur Hunter, JR., SungYe Kim, Mike Macpherson, Elmoustapha Ould-Ahmed-Vall, William Sadler, Lakshminarayanan Striramassarma, Vikranth Vemulapalli
  • Patent number: 10904117
    Abstract: Techniques for providing insights for web service providers are disclosed. In some embodiments, a system, process, and/or computer program product for providing insights for web service providers includes monitoring user activities on a web site; generating a dashboard for displaying a summary of the monitored user activities on the web site; and generating a recommendation for improving performance of the web site for display on the dashboard. For example, the recommendation can be for improving performance of search results on the web site and/or for improving content navigation on the web site.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: January 26, 2021
    Assignee: BloomReach Inc.
    Inventors: Wai Hung Wong, Nishant Deshpande, Pradeep Muthukrishnan, Vaibhav Avinash Chidrewar, Charlie Luo, Rahul Bhandari, Ashutosh Garg
  • Patent number: 10853562
    Abstract: A system and method for transferring annotations associated with a media file. An annotation associated with a media file is indexed to a first instance of that media file. By comparing features of the two instances, a mapping is created between the first instance of the media file and a second instance of the media file. The annotation can be indexed to the second instance using the mapping between the first and second instances. The annotation can be processed (displayed, stored, or modified) based on the index to the second instance.
    Type: Grant
    Filed: April 15, 2019
    Date of Patent: December 1, 2020
    Assignee: Google LLC
    Inventors: Mayur Datar, Ashutosh Garg, Vibhu Mittal
  • Patent number: 10810275
    Abstract: Techniques for performing query-dependent and content-class (e.g., with product class as a subset, in which content class can be based on a product class in an example implementation) based ranking are disclosed in accordance with some embodiments. In some embodiments, a process for performing query-dependent and content-class based ranking includes receiving a query for a search for content on a web site; performing a query-dependent and content-class based ranking of content available on the web site (e.g., using a processor); and returning a ranked list of content based at least in part on the query-dependent and content-class based ranking of content available on the web site in response to the query.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: October 20, 2020
    Assignee: BloomReach Inc.
    Inventors: Ashutosh Garg, Romil Shah, Vinodh Kumar, Ram Gopalan, Sumeet Khullar
  • Patent number: 10803421
    Abstract: A method and system relating to determine a match between a candidate and a job position for an enterprise, the method and system including receiving an enriched talent profile associated with the candidate, the enriched talent profile comprising a talent profile of the candidate derived from a first data source of the enterprise, and one or more supplemental data items obtained from a second data source independent from the first data source, generating a calibrated job profile for the job position, the calibrated job profile comprising information, and executing a machine learning module using the enriched talent profile and the calibrated job profile as inputs to determine a match score between the candidate and the job position.
    Type: Grant
    Filed: August 31, 2019
    Date of Patent: October 13, 2020
    Assignee: Eightfold AI Inc.
    Inventors: Ashutosh Garg, Varun Kacholia
  • Patent number: 10783194
    Abstract: Methods, systems, and apparatus, including computer program products, for assisting users in performing searches. In one aspect, a query for a search session is received from a user device. A first set of search results responsive to the query is provided to the user device. Search results interaction data are received from the user device that identifies actions that are in response to the search results and taken at the user device. The search results interaction data are analyzed to determine that a remedial search operation should be performed, the remedial search operation determining a second set of search results responsive to the query and providing the second set of search results to the user device for presentation to the user.
    Type: Grant
    Filed: February 1, 2018
    Date of Patent: September 22, 2020
    Assignee: Google LLC
    Inventors: Ashutosh Garg, Kedar Dhamdhere
  • Patent number: 10754651
    Abstract: Embodiments are generally directed to register bank conflict reduction for multi-threaded processor execution units. An embodiment of an apparatus includes a processor including one or more execution units (EUs), at least a first execution unit (EU) to process a plurality of threads, the first EU including a register file including multiple register banks with each register bank including multiple registers, and one or more read multiplexers to read registers from the register file, wherein attempting to read more than one register from a single register bank of the register file in a same clock cycle generates a register bank conflict. Registers for each thread for the first EU are distributed across the registers banks within the register file such that a first register for a first thread of the plurality of threads and a following second register for the first thread are located in different register banks within the register file.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: August 25, 2020
    Assignee: INTEL CORPORATION
    Inventors: Chandra Gurram, Subramaniam Maiyuran, Buqi Cheng, Ashutosh Garg, Guei-Yuan Lueh, Wei-Yu Chen
  • Patent number: 10719562
    Abstract: Techniques for providing a distributed and fast data storage layer for large scale web data services are disclosed. In some embodiments, a distributed data storage layer for web data services includes storing web related data for a plurality of merchants in the distributed data storage layer; and copying on demand a data store and a search index for web related data for a first merchant to perform a job for updating the web related data for the first merchant.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: July 21, 2020
    Assignee: BloomReach Inc.
    Inventors: Prateek Gupta, Praveen K. Patnala, Amit Aggarwal, Ashutosh Garg, Gurashish Singh Brar, Kannan Nitin Sharma, Manojit Sarkar, Shao-Chuan Wang