Patents by Inventor Ashutosh Mishra
Ashutosh Mishra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12254178Abstract: A method to handle insufficient on-chip memory capacity in decompressors is disclosed. In one embodiment, such a method includes executing, by a decompressor configured to decompress data, an instruction configured to copy data from a source position within a data stream to a destination position within the data stream. The method determines whether the source position currently resides within an on-chip buffer of the decompressor. In the event the source position does not currently reside within the on-chip buffer of the decompressor, the method writes arbitrary placeholder data to the destination position and adds the instruction to a patch buffer. At a later point in time, the method retrieves the instruction from the patch buffer and executes the instruction by retrieving the data from the source position and overwriting the arbitrary placeholder data at the destination position with the data. A corresponding system and computer program product are also disclosed.Type: GrantFiled: June 30, 2023Date of Patent: March 18, 2025Assignee: International Business Machines CorporationInventors: Bulent Abali, Matthias Klein, Ashutosh Mishra, Girish Gopala Kurup
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Publication number: 20250004638Abstract: A method to handle insufficient on-chip memory capacity in decompressors is disclosed. In one embodiment, such a method includes executing, by a decompressor configured to decompress data, an instruction configured to copy data from a source position within a data stream to a destination position within the data stream. The method determines whether the source position currently resides within an on-chip buffer of the decompressor. In the event the source position does not currently reside within the on-chip buffer of the decompressor, the method writes arbitrary placeholder data to the destination position and adds the instruction to a patch buffer. At a later point in time, the method retrieves the instruction from the patch buffer and executes the instruction by retrieving the data from the source position and overwriting the arbitrary placeholder data at the destination position with the data. A corresponding system and computer program product are also disclosed.Type: ApplicationFiled: June 30, 2023Publication date: January 2, 2025Applicant: International Business Machines CorporationInventors: Bulent Abali, Matthias Klein, Ashutosh Mishra, Girish Gopala Kurup
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Publication number: 20240378988Abstract: A wireless communication system for exchanging messages between a patient support apparatus and a headwall unit includes intelligence built into either or both of these devices (and/or a server) for detecting when a mismatch occurs between the communication capabilities of the patient support apparatus and those of the headwall unit. A warning is issued in those situations where a caregiver is relying on communication abilities that are not present in one or both of the devices. Examples of such situations include, but are not limited to, a nurse call cable not being coupled between the patient support apparatus and the nurse call system when the patient support apparatus does not have the capability to wirelessly communicate with the nurse call system. Alternatively, or additionally, the headwall unit may issue an alert to a nurse call system if it detects one or more conditions that warrant immediate caregiver attention.Type: ApplicationFiled: July 23, 2024Publication date: November 14, 2024Inventors: Jerald A. Trepanier, Alexander Josef Bodurka, Krishna Sandeep Bhimavarapu, Vinod Prakash Bhatt, Ashutosh Mishra
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Publication number: 20240311260Abstract: A computer system, computer readable storage medium, and computer-implemented method for dynamically degrading a link between multiple processing devices to facilitate uninterrupted service between the multiple processing devices. The method includes determining a number of undegraded lanes within the link. The method also includes determining, subject to the number of undegraded lanes, a first operational degrade mode for the link. The method further includes initiating a retrain of the link to a second operational degrade mode. The method also includes dynamically, subject to the first degrade mode of operation, determining one or more message packet types to transmit through the link during the link retrain, thereby facilitating uninterrupted service between the multiple processing devices.Type: ApplicationFiled: March 13, 2023Publication date: September 19, 2024Inventors: Rajat Rao, Patrick James Meaney, Ashutosh Mishra, Jason Andrew Thompson, Nandini Gaadam Nagaraj
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Patent number: 12046124Abstract: A wireless communication system for exchanging messages between a patient support apparatus and a headwall unit includes intelligence built into either or both of these devices (and/or a server) for detecting when a mismatch occurs between the communication capabilities of the patient support apparatus and those of the headwall unit. A warning is issued in those situations where a caregiver is relying on communication abilities that are not present in one or both of the devices. Examples of such situations include, but are not limited to, a nurse call cable not being coupled between the patient support apparatus and the nurse call system when the patient support apparatus does not have the capability to wirelessly communicate with the nurse call system. Alternatively, or additionally, the headwall unit may issue an alert to a nurse call system if it detects one or more conditions that warrant immediate caregiver attention.Type: GrantFiled: May 26, 2022Date of Patent: July 23, 2024Assignee: Stryker CorporationInventors: Jerald A. Trepanier, Alexander Josef Bodurka, Krishna Sandeep Bhimavarapu, Vinod Prakash Bhatt, Ashutosh Mishra
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Publication number: 20240202117Abstract: A computer-implemented method, according to one embodiment, includes determining that a first predetermined pattern is to be written to a first cache line of a cache. In response to the determination, a first bit is set in a first directory instead of writing the first predetermined pattern in the first cache line. The first bit is associated with the first cache line in the first directory. A computer program product, according to another embodiment, includes a computer readable storage medium having program instructions embodied therewith. The program instructions are readable and/or executable by a computer to cause the computer to perform the foregoing method. A system, according to another embodiment, includes a processor, and logic integrated with the processor, executable by the processor, or integrated with and executable by the processor. The logic is configured to perform the foregoing method.Type: ApplicationFiled: December 16, 2022Publication date: June 20, 2024Inventors: Bulent Abali, Alper Buyuktosunoglu, Ashutosh Mishra, David Trilla Rodriguez, Craig R. Walters
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Patent number: 11907074Abstract: Embodiments of the invention are directed to a computer-implemented method of operating a data transmission system. The data transmission system includes a transmitter and a receiver. The computer-implemented method includes using the transmitter to send serialized data from the transmitter through a plurality of lanes to the receiver. The transmitter sends the serialized data at a first serialization ratio. The receiver is configured to receive and load the serialized data at a second deserialization ratio, wherein the first serialization ration is greater than the second deserialization ratio.Type: GrantFiled: September 24, 2021Date of Patent: February 20, 2024Assignee: International Business Machines CorporationInventors: Patrick James Meaney, Ashutosh Mishra, Paul Allen Ganfield, Christian Jacobi, Logan Ian Friedman, Jentje Leenstra, Glenn David Gilda, Michael B. Spear
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Patent number: 11792303Abstract: Various embodiments are provided herein for compressing data in latency-critical processor links of a computing system in a computing environment. One or more cache lines may be dynamically compressed at a lowest level of a networking stack based on one or more of a plurality of parameters prior to transferring a single-cache line, where the networking stack includes a framer and a data link layer.Type: GrantFiled: September 30, 2022Date of Patent: October 17, 2023Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Rajat Rao, Ashutosh Mishra, Bulent Abali, Alper Buyuktosunoglu
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Low-latency, high-availability and high-speed SerDes interface having multiple synchronization modes
Patent number: 11646861Abstract: A computer-implemented method includes using a transmitter to send data from the transmitter through a plurality of lanes to a receiver using a synchronous operation mode that includes sending the data from the transmitter through the plurality of lanes to the receiver in a synchronous transmission manner that relies on an alignment between a transmitter clock frequency and a receiver clock frequency. A synchronous operation performance analysis (SOPA) is performed during the synchronous operation mode. A switch from the synchronous operation mode to an asynchronous operation mode is made based on a result of performing the SOPA. The asynchronous operation mode includes sending the data from the transmitter through the plurality of lanes to the receiver without requiring alignment between the transmitter clock frequency and the receiver clock frequency.Type: GrantFiled: September 24, 2021Date of Patent: May 9, 2023Assignee: International Business Machines CorporationInventors: Patrick James Meaney, Ashutosh Mishra, Paul Allen Ganfield, Christian Jacobi, Logan Ian Friedman, Jentje Leenstra, Glenn David Gilda, Jason Andrew Thompson, Yvonne Hanson Kleppel -
Publication number: 20230115533Abstract: Embodiments of the invention are directed to a computer-implemented method of operating a data transmission system. The data transmission system includes a transmitter and a receiver. The computer-implemented method includes using the transmitter to send serialized data from the transmitter through a plurality of lanes to the receiver. The transmitter sends the serialized data at a first serialization ratio. The receiver is configured to receive and load the serialized data at a second deserialization ratio, wherein the first serialization ration is greater than the second deserialization ratio.Type: ApplicationFiled: September 24, 2021Publication date: April 13, 2023Inventors: Patrick James Meaney, Ashutosh Mishra, Paul Allen Ganfield, Christian Jacobi, Logan Ian Friedman, Jentje Leenstra, Glenn David Gilda, Michael B. Spear
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LOW-LATENCY, HIGH-AVAILABILITY AND HIGH-SPEED SERDES INTERFACE HAVING MULTIPLE SYNCHRONIZATION MODES
Publication number: 20230098514Abstract: A computer-implemented method includes using a transmitter to send data from the transmitter through a plurality of lanes to a receiver using a synchronous operation mode that includes sending the data from the transmitter through the plurality of lanes to the receiver in a synchronous transmission manner that relies on an alignment between a transmitter clock frequency and a receiver clock frequency. A synchronous operation performance analysis (SOPA) is performed during the synchronous operation mode. A switch from the synchronous operation mode to an asynchronous operation mode is made based on a result of performing the SOPA. The asynchronous operation mode includes sending the data from the transmitter through the plurality of lanes to the receiver without requiring alignment between the transmitter clock frequency and the receiver clock frequency.Type: ApplicationFiled: September 24, 2021Publication date: March 30, 2023Inventors: Patrick James Meaney, Ashutosh Mishra, Paul Allen Ganfield, Christian Jacobi, Logan Ian Friedman, Jentje Leenstra, Glenn David Gilda, Jason Andrew Thompson, Yvonne Hanson Kleppel -
Publication number: 20220383729Abstract: A wireless communication system for exchanging messages between a patient support apparatus and a headwall unit includes intelligence built into either or both of these devices (and/or a server) for detecting when a mismatch occurs between the communication capabilities of the patient support apparatus and those of the headwall unit. A warning is issued in those situations where a caregiver is relying on communication abilities that are not present in one or both of the devices. Examples of such situations include, but are not limited to, a nurse call cable not being coupled between the patient support apparatus and the nurse call system when the patient support apparatus does not have the capability to wirelessly communicate with the nurse call system. Alternatively, or additionally, the headwall unit may issue an alert to a nurse call system if it detects one or more conditions that warrant immediate caregiver attention.Type: ApplicationFiled: May 26, 2022Publication date: December 1, 2022Inventors: Jerald A. Trepanier, Alexander Josef Bodurka, Krishna Sandeep Bhimavarapu, Vinod Prakash Bhatt, Ashutosh Mishra
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Patent number: 10831497Abstract: An instruction to perform a function of a plurality of functions is obtained. The instruction is a single architected instruction of an instruction set architecture that complies to an industry standard for compression. The instruction is executed, and the executing includes performing the function specified by the instruction. The performing includes, based on the function being a compression function or a decompression function, transforming state of input data between an uncompressed form of the input data and a compressed form of the input data to provide a transformed state of data accessing. During performing the function, history relating to the function is accessed. The history is to be used in transforming the state of input data between the uncompressed form and the compressed form.Type: GrantFiled: January 31, 2019Date of Patent: November 10, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce C. Giamei, Anthony T. Sofia, Matthias Klein, Simon Weishaupt, Mark S. Farrell, Timothy Slegel, Ashutosh Mishra, Christian Jacobi
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Publication number: 20200249948Abstract: An instruction to perform a function of a plurality of functions is obtained. The instruction is a single architected instruction of an instruction set architecture that complies to an industry standard for compression. The instruction is executed, and the executing includes performing the function specified by the instruction. The performing includes, based on the function being a compression function or a decompression function, transforming state of input data between an uncompressed form of the input data and a compressed form of the input data to provide a transformed state of data accessing. During performing the function, history relating to the function is accessed. The history is to be used in transforming the state of input data between the uncompressed form and the compressed form.Type: ApplicationFiled: January 31, 2019Publication date: August 6, 2020Inventors: Bruce C. Giamei, Anthony T. Sofia, Matthias Klein, Simon Weishaupt, Mark S. Farrell, Timothy Slegel, Ashutosh Mishra, Christian Jacobi
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Patent number: 10630312Abstract: A DEFLATE Conversion Call general-purpose processor instruction. An instruction is obtained by a general-purpose processor of the computing environment. The instruction is a single architected instruction of an instruction set architecture that complies to an industry standard for compression. The instruction is executed, and the executing includes transforming, based on a function to be performed by the instruction being a compression function or a decompression function, state of input data between an uncompressed form of the input data and a compressed form of the input data to provide a transformed state of data. The transformed state of the data is provided as output to be used in performing a task.Type: GrantFiled: January 31, 2019Date of Patent: April 21, 2020Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bruce C. Giamei, Matthias Klein, Timothy Slegel, Mark S. Farrell, Anthony T. Sofia, Simon Weishaupt, Ashutosh Mishra
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Patent number: 8934840Abstract: Systems, methods, and other embodiments associated with performing arbitration among a plurality of driver circuits in a communication device are described. According to one embodiment, an apparatus includes a first source configured to transmit first packets and a second source configured to transmit second packets. The arbiter logic is configured to input a thermal management mode that is selected based, at least in part, on a thermal consequence of simultaneous transmission of packets from the first source and the second source. The arbiter logic is configured to select either i) the first packets, ii) the second packets, or iii) both the first packets and the second packets for transmission based, at least in part, on the thermal management mode input by the arbiter logic.Type: GrantFiled: December 18, 2012Date of Patent: January 13, 2015Assignee: Marvell International Ltd.Inventors: Ken Yeung, Ashutosh Mishra, Harish Ramamurthy, Hao Zhang