Patents by Inventor Ashutosh Sinha

Ashutosh Sinha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12723543
    Abstract: A heat exchanger assembly includes an inlet manifold, an outlet manifold, a plate extending from the inlet manifold to the outlet manifold, the plate defining a plate channel, a bypass structure defining a bypass channel in fluid communication with the outlet manifold and with a heated fluid supply, and a fin extending between the bypass channel and the plate, the fin defining a fin channel fluidly connecting the bypass channel to the plate channel.
    Type: Grant
    Filed: June 3, 2025
    Date of Patent: September 1, 2026
    Assignees: General Electric Company, General Electric Deutschland Holding GmbH
    Inventors: Viorel-Marian Barbu, Hojjat Nasr, Michael Vadnais, Atanu Saha, Ashutosh Sinha, Kevin Edward Hinderliter
  • Patent number: 9219625
    Abstract: A decision feedback equalization slicer for ultra-high-speed backplane Serializer/Deserializer (SerDes) with improved latch sensitivity. A first regeneration stage can be configured in association with a second regeneration stage to compensate for channel impairment such as Inter-symbol interference due to channel loss, reflections due to impedance mismatch, and cross-talk interference from neighboring electrical channels. The first regeneration stage includes two first stage slicers corresponding to a set of speculative decision (+h1 and ?h1). A multiplexer can be placed at an input port of the second regeneration stage to select the set of speculative decision based on previous decision in order to save hardware and power. The DFE slicer samples the Input signal, regenerates the sampled data, stores the data on storage element like RS-latch or flip-flop, and presets the regeneration nodes to high or low values in preparation for sampling the next input data.
    Type: Grant
    Filed: April 23, 2014
    Date of Patent: December 22, 2015
    Assignee: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
    Inventor: Ashutosh Sinha
  • Publication number: 20150312060
    Abstract: A decision feedback equalization slicer for ultra-high-speed backplane Serializer/Deserializer (SerDes) with improved latch sensitivity. A first regeneration stage can be configured in association with a second regeneration stage to compensate for channel impairment such as inter-symbol interference due to channel loss, reflections due to impedance mismatch, and cross-talk interference from neighboring electrical channels. The first regeneration stage includes two first stage slicers corresponding to a set of speculative decision (+h1 and ?h1). A multiplexer can be placed at an input port of the second regeneration stage to select the set of speculative decision based on previous decision in order to save hardware and power. The DFE slicer samples the input signal, regenerates the sampled data, stores the data on storage element like RS-latch or flip-flop, and presets the regeneration nodes to high or low values in preparation for sampling the next input data.
    Type: Application
    Filed: April 23, 2014
    Publication date: October 29, 2015
    Applicant: LSI Corporation
    Inventor: Ashutosh Sinha