Abstract: A hybrid emulation system includes a hardware emulation system, a simulation system, and a co-simulation interface. The hardware emulation system emulates a first portion of a design under test (DUT) during a hybrid emulation. The emulation runs in a first time domain local to the hardware emulation system. The simulation system simulates a second portion of the DUT during the hybrid emulation. The simulation runs in a second time domain local to the simulation system. The first time domain and the second time domain are unsynchronized. The co-simulation interface is coupled to the simulation system and the hardware emulation system. The co-simulation interface communicates transactions and events between the hardware emulation system and the simulation system. For each transaction, the co-simulation interface captures a transaction time in the first time domain, and for each event, the co-simulation interface captures an event time in the first time domain.

Abstract: A hybrid emulation system and method for hybrid emulation of a design under test (DUT). The DUT has system memory logically segmented into a plurality of memory blocks. The hybrid emulation system comprises a hardware emulation system to emulate a first portion of the DUT during the hybrid emulation. The hybrid emulation system also comprises a simulation system to simulate a second portion of the DUT during the hybrid emulation. At least one of the hardware emulation system or the simulation system is configured to assign a memory block of the plurality of memory blocks to one of the hardware emulation system or the simulation system based on memory access statistics describing accesses to the memory block during the hybrid emulation.

Abstract: The present patent document relates to a method and apparatus for enabling direct memory access into a target memory subsystem of an electronic system modeled in dual abstractions while maintaining coherency. The portions of the memory subsystem shared between the first abstraction and the second abstraction are shadowed in both abstractions, allowing either abstraction to coherently access memory written by the other. Flags associated with memory pages of the memory subsystem are set to indicate which abstraction has most recently updated the memory page. Where the first abstraction is SystemC using TLM2, DMI access may be selectively enabled to facilitate faster access from SystemC, and DMI access disabled when an access from the second abstraction is detected in order to invoke coherency procedures. This allows coherency to be maintained and may enable faster software code execution where most access are DMI accesses from SystemC.

Abstract: The present patent document relates to a method and apparatus for maintaining coherency in a memory subsystem of an electronic system modeled in dual abstractions. The portions of the memory subsystem shared between the first abstraction and the second abstraction are shadowed in both abstractions, allowing either abstraction to coherently access memory written by the other. The memory subsystem can also reside solely in a first abstraction, where the second abstraction will synchronize to the first abstraction to access the memory subsystem. Flags associated with memory pages of the memory subsystem are set to indicate which abstraction has most recently updated the memory page. Prior to accessing a memory page, the system will check the flags, copying the contents of the memory in the other abstraction as needed to maintain coherency. The abstractions can operate either synchronously or asynchronously.