Patents by Inventor ASHVINKUMAR NAMJOSHI

ASHVINKUMAR NAMJOSHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems and methods for providing dynamic cache extension in a multi-cluster heterogeneous processor architecture
    Patent number: 9697124
    Abstract: A dynamic cache extension in a multi-cluster heterogeneous processor architecture is described. One embodiment is a system comprising a first processor cluster having a first level two (L2) cache and a second processor cluster having a second L2 cache. The system further comprises a controller in communication with the first and second L2 caches. The controller receives a processor workload input and a cache workload input from the first processor cluster. Based on processor workload input and the cache workload input, the cache controller determines whether a current task associated with the first processor cluster is limited by a size threshold of the first L2 cache or a performance threshold of the first processor cluster. If the current task is limited by the size threshold of the first L2 cache, the controller uses at least a portion of the second L2 cache as an extension of the first L2 cache.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: July 4, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Hee Jun Park, Krishna Vsssr Vanka, Sravan Kumar Ambapuram, Shirish Kumar Agarwal, Ashvinkumar Namjoshi, Harshad Bhutada
  • SYSTEMS AND METHODS FOR PROVIDING DYNAMIC CACHE EXTENSION IN A MULTI-CLUSTER HETEROGENEOUS PROCESSOR ARCHITECTURE
    Publication number: 20160203083
    Abstract: A dynamic cache extension in a multi-cluster heterogeneous processor architecture is described. One embodiment is a system comprising a first processor cluster having a first level two (L2) cache and a second processor cluster having a second L2 cache. The system further comprises a controller in communication with the first and second L2 caches. The controller receives a processor workload input and a cache workload input from the first processor cluster. Based on processor workload input and the cache workload input, the cache controller determines whether a current task associated with the first processor cluster is limited by a size threshold of the first L2 cache or a performance threshold of the first processor cluster. If the current task is limited by the size threshold of the first L2 cache, the controller uses at least a portion of the second L2 cache as an extension of the first L2 cache.
    Type: Application
    Filed: January 13, 2015
    Publication date: July 14, 2016
    Inventors: HEE JUN PARK, KRISHNA VSSSR VANKA, SRAVAN KUMAR AMBAPURAM, SHIRISH KUMAR AGARWAL, ASHVINKUMAR NAMJOSHI, HARSHAD BHUTADA