Patents by Inventor Ashwani K. Malhotra
Ashwani K. Malhotra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7851911Abstract: A semiconductor chip for forming the same. The semiconductor chip includes M regular solder bump structures and N monitor solder bump structures, M and N being positive integers. If a flip chip process is performed for the semiconductor chip, then the N monitor solder bump structures are more sensitive to a cool-down stress than the M regular solder bump structures. The cool-down stress results from a cool-down step of the flip chip process. Each of the M regular solder bump structures is electrically connected to either a power supply or a device of the semiconductor chip. Each of the N monitor solder bump structures is not electrically connected to a power supply or a device of the semiconductor chip.Type: GrantFiled: March 2, 2010Date of Patent: December 14, 2010Assignee: International Business Machines CorporationInventors: Charles F. Carey, Bernt Julius Hansen, Ashwani K. Malhotra, David L. Questad, Wolfgang Sauter
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Publication number: 20100155943Abstract: A semiconductor chip for forming the same. The semiconductor chip includes M regular solder bump structures and N monitor solder bump structures, M and N being positive integers. If a flip chip process is performed for the semiconductor chip, then the N monitor solder bump structures are more sensitive to a cool-down stress than the M regular solder bump structures. The cool-down stress results from a cool-down step of the flip chip process. Each of the M regular solder bump structures is electrically connected to either a power supply or a device of the semiconductor chip. Each of the N monitor solder bump structures is not electrically connected to a power supply or a device of the semiconductor chip.Type: ApplicationFiled: March 2, 2010Publication date: June 24, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Charles F. Carey, Bernt Julius Hansen, Ashwani K. Malhotra, David L. Questad, Wolfgang Sauter
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Patent number: 7674637Abstract: A semiconductor chip and methods for forming the same. The semiconductor chip includes M regular solder bump structures and N monitor solder bump structures, M and N being positive integers. If a flip chip process is performed for the semiconductor chip, then the N monitor solder bump structures are more sensitive to a cool-down stress than the M regular solder bump structures. The cool-down stress results from a cool-down step of the flip chip process. Each of the M regular solder bump structures is electrically connected to either a power supply or a device of the semiconductor chip. Each of the N monitor solder bump structures is not electrically connected to a power supply or a device of the semiconductor chip.Type: GrantFiled: May 17, 2007Date of Patent: March 9, 2010Assignee: International Business Machines CorporationInventors: Charles F. Carey, Bernt Julius Hansen, Ashwani K. Malhotra, David L. Questad, Wolfgang Sauter
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Publication number: 20080286886Abstract: A semiconductor chip and methods for forming the same. The semiconductor chip includes M regular solder bump structures and N monitor solder bump structures, M and N being positive integers. If a flip chip process is performed for the semiconductor chip, then the N monitor solder bump structures are more sensitive to a cool-down stress than the M regular solder bump structures. The cool-down stress results from a cool-down step of the flip chip process. Each of the M regular solder bump structures is electrically connected to either a power supply or a device of the semiconductor chip. Each of the N monitor solder bump structures is not electrically connected to a power supply or a device of the semiconductor chip.Type: ApplicationFiled: May 17, 2007Publication date: November 20, 2008Inventors: Charles F. Carey, Bernt Julius Hansen, Ashwani K. Malhotra, David L. Questad, Wolfgang Sauter
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Patent number: 6241868Abstract: A method for electroplating a film onto a substrate. Electrical power is supplied to the plating surface through electrical contact made to contact pads on the underside of the substrate. Contact to the contact pads is made within a liquid-tight region. The contact pads are connected to the plating surface through the substrate. Because the contact scheme is provided within a liquid-tight region on the underside of the substrate, the contacts do not erode or become plated, nor do they consume an area of the plating surface.Type: GrantFiled: March 31, 2000Date of Patent: June 5, 2001Assignee: International Business Machines CorporationInventors: Glen N. Biggs, Donald M. Brewer, James E. Fluegel, Suryanarayana Kaja, Ashwani K. Malhotra, Phillip W. Palmatier
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Patent number: 6235412Abstract: A process for producing a terminal metal pad structure electrically interconnecting a package and other components. More particularly, the invention encompasses a process for producing a plurality of corrosion-resistant terminal metal pads. Each pad includes a base pad containing copper which is encapsulated within a series of successively electroplated metal encapsulating films to produce a corrosion-resistant terminal metal pad.Type: GrantFiled: April 6, 2000Date of Patent: May 22, 2001Assignee: International Business Machines CorporationInventors: Tien-Jen Cheng, Ajay P. Giri, Ashwani K. Malhotra, John R. Pennacchia, Eric D. Perfecto, Roy Yu
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Patent number: 6188124Abstract: A semiconductor arrangement having a first active region and a dummy region on a surface of a substrate. The first active region and the dummy region are spaced from one another without any contact, and the dummy region is closer to an edge of the surface of the substrate in comparison to the first active region. Formed on the dummy region, first active region, and a portion of the substrate surface is a dielectric layer. The surface of the dielectric layer has an inactive portion and an active portion. A mask is disposed on the dielectric layer such that the mask contacts the inactive portion and does not contact the active portion.Type: GrantFiled: July 14, 1999Date of Patent: February 13, 2001Assignee: International Business Machines CorporationInventors: Gregory S. Boettcher, Robert P. Katz, Ashwani K. Malhotra, James Wood
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Patent number: 6183588Abstract: A process for fabricating and releasing a thin-film structure from a primary carrier for further processing. The thin-film structure is built on a metal interconnect disposed on a dielectric layer which, in turn, is deposited on a primary carrier. The thin-film structure and metal interconnect are released from the dielectric layer and primary carrier along a release interface defined between the metal interconnect and the dielectric film. Release is accomplished by disturbing the interface, either by laser ablation or dicing.Type: GrantFiled: December 14, 1999Date of Patent: February 6, 2001Assignee: International Business Machines CorporationInventors: Kimberley A. Kelly, Ashwani K. Malhotra, Eric D. Perfecto, Roy Yu
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Patent number: 6143117Abstract: A process for fabricating and releasing a thin-film structure from a primary carrier for further processing. The thin-film structure is built on a metal interconnect disposed on a dielectric layer which, in turn, is deposited on a primary carrier. The thin-film structure and metal interconnect are released from the dielectric layer and primary carrier along a release interface defined between the metal interconnect and the dielectric film. Release is accomplished by disturbing the interface, either by laser ablation or dicing.Type: GrantFiled: December 14, 1999Date of Patent: November 7, 2000Assignee: International Business Machines CorporationInventors: Kimberley A. Kelly, Ashwani K. Malhotra, Eric D. Perfecto, Roy Yu
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Patent number: 6083375Abstract: A process for producing a terminal metal pad structure electrically interconnecting a package and other components. More particularly, the invention encompasses a process for producing a plurality of corrosion-resistant terminal metal pads. Each pad includes a base pad containing copper which is encapsulated within a series of successively electroplated metal encapsulating films to produce a corrosion-resistant terminal metal pad.Type: GrantFiled: November 2, 1998Date of Patent: July 4, 2000Assignee: International Business Machines CorporationInventors: Tien-Jen Cheng, Ajay P. Giri, Ashwani K. Malhotra, John R. Pennacchia, Eric D. Perfecto, Roy Yu
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Patent number: 6077405Abstract: A method and apparatus for electroplating a film onto a substrate. Electrical power is supplied to the plating surface through electrical contact made to contact pads on the underside of the substrate. Contact to the contact pads is made within a liquid-tight region. The contact pads are connected to the plating surface through the substrate. Because the contact scheme is provided within a liquid-tight region on the underside of the substrate, the contacts do not erode or become plated, nor do they consume an area of the plating surface.Type: GrantFiled: October 28, 1998Date of Patent: June 20, 2000Assignee: International Business Machines CorporationInventors: Glen N. Biggs, Donald M. Brewer, James E. Fluegel, Suryanarayana Kaja, Ashwani K. Malhotra, Phillip W. Palmatier
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Patent number: 6036809Abstract: A process for fabricating and releasing a thin-film structure from a primary carrier for further processing. The thin-film structure is built on a metal interconnect disposed on a dielectric layer which, in turn, is deposited on a primary carrier. The thin-film structure and metal interconnect are released from the dielectric layer and primary carrier along a release interface defined between the metal interconnect and the dielectric film. Release is accomplished by disturbing the interface, either by laser ablation or dicing.Type: GrantFiled: February 16, 1999Date of Patent: March 14, 2000Assignee: International Business Machines CorporationInventors: Kimberley A. Kelly, Ashwani K. Malhotra, Eric D. Perfecto, Roy Yu
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Patent number: 6002267Abstract: A test pad is formed outside an array of pads included in connection structures such as pin mounting pads to which connection pins may be brazed in, for example, bottom side metallurgy of a multi-layer modular electronic package. In-line voltage plane testing may then be accomplished through temporary connections to the test pads for any desired layer, such as top side metallurgy distribution layers, while protecting the pin-mounting pads from physical and/or chemical damage or contamination during manufacturing processes for addition of layers to the electrical interconnection structure of the multi-layer module.Type: GrantFiled: July 23, 1997Date of Patent: December 14, 1999Assignee: International Business Machines Corp.Inventors: Ashwani K. Malhotra, John R. Pennacchia, Ronald R. Shields, Thomas A. Wassick