Abstract: Various implementations described herein refer to a device having a cell structure with multiple transistors including active n-type transistors and active p-type transistors disposed together within a cell boundary. The active n-type transistors may have a first diffusion region formed within the cell boundary at a first end of the cell structure. The active p-type transistors may have a second diffusion region formed within the cell boundary at a second end of the cell structure. The active p-type transistors may have a vacated region cut-out from the second diffusion region, and/or the active n-type transistors may have a vacated region cut-out from the first diffusion region.

Abstract: Subject matter disclosed herein relates generally to semiconductor devices, and, more particularly, to semiconductor device layout, including, for example, cells incorporating finFET-type devices. A semiconductor device may include finFET-type devices, for example, arranged in a standard cell architecture including fractional-height cells.

Abstract: Apparatus for converting a first input signal from a first voltage domain to an output signal for a second voltage domain, the apparatus configured to operate within the first voltage domain or within the second voltage domain. The apparatus comprising input driver circuitry configured to generate second input signal based on the first input signal and a control signal received by input driver circuitry. The apparatus also comprising selection circuitry configured to generate a selection signal based on the control signal. The apparatus also comprising cross-coupled circuitry configured to generate a level-shifted signal at an intermediate node based on the first input signal, the second input signal, and the selection signal. The cross-coupled circuitry comprises a first pair of parallel transistors and a second pair of parallel transistors. The apparatus further comprising output driver circuitry configured to generate output signal for the second voltage domain based on the level-shifted signal.

Abstract: An integrated circuit 2 has data processing circuitry processing a data signal passing along a data path 14. Clocked circuitry coupled to the data processing circuitry serves to regulate passage of the data signal along the data path. The data signal is supplied at a data signal voltage amplitude and the clock signal is supplied at a different clock signal voltage amplitude. The clock signal voltage amplitude is higher than the data signal voltage amplitude. A separate clock signal power supply grid 12 is provided in addition to the data power supply grid 10.

Abstract: An integrated circuit 2 has data processing circuitry processing a data signal passing along a data path 14. Clocked circuitry coupled to the data processing circuitry serves to regulate passage of the data signal along the data path. The data signal is supplied at a data signal voltage amplitude and the clock signal is supplied at a different clock signal voltage amplitude. The clock signal voltage amplitude is higher than the data signal voltage amplitude. A separate clock signal power supply grid 12 is provided in addition to the data power supply grid 10.