Patents by Inventor Ashwani Oberai

Ashwani Oberai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7293130
    Abstract: A method and system is provided for a multi-level memory. The system includes an internal memory and an external memory. Data packets are received through one or more input ports and initially stored in the internal memory. A control unit determines whether there is congestion of resources within the system and transfers data packets to external memory to ease the congestion. Data packets are eventually transferred from the internal or external memory to one or more output ports.
    Type: Grant
    Filed: May 29, 2002
    Date of Patent: November 6, 2007
    Assignee: Intel Corporation
    Inventors: Rahul Saxena, Hitesh Rastogi, Ashwani Oberai
  • Publication number: 20060117114
    Abstract: A method according to one embodiment may include transmitting a plurality of packets through control pipeline circuitry of an integrated circuit of a switch. The control pipeline circuitry may be capable of making a plurality of memory requests to memory of the switch in response to the plurality of packets. The method may further comprise staggering the plurality of memory requests so that each of the plurality of memory requests occurs during a different one of a plurality of time slots. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.
    Type: Application
    Filed: November 29, 2004
    Publication date: June 1, 2006
    Inventors: Rohit Verma, Muraleedhara Navada, Miguel Guerrero, Ashwani Oberai
  • Publication number: 20050024241
    Abstract: A method and apparatus for generating Gray code for any even count value to enable efficient pointer exchange mechanisms in asynchronous FIFO's. Allowing Gray code for any range of even count values provides the benefit of decreasing metastability when exchanging pointers for FIFO buffers in asynchronous environments. Utilizing the Gray code adjacency principle, which provides that only one bit changes for any successive numbers, in a larger class of numbers than previously utilized, decreases metastability.
    Type: Application
    Filed: August 24, 2004
    Publication date: February 3, 2005
    Inventors: Ashwani Oberai, Kavitha Prasad, Sreenath Kurupati
  • Patent number: 6801143
    Abstract: A method and apparatus for generating Gray code for any even count value to enable efficient pointer exchange mechanisms in asynchronous FIFO's. Allowing Gray code for any range of even count values provides the benefit of decreasing metastability when exchanging pointers for FIFO buffers in asynchronous environments. Utilizing the Gray code adjacency principle, which provides that only one bit changes for any successive numbers, in a larger class of numbers than previously utilized, decreases metastability.
    Type: Grant
    Filed: June 28, 2002
    Date of Patent: October 5, 2004
    Assignee: Intel Corporation
    Inventors: Ashwani Oberai, Kavitha A. Prasad, Sreenath Kurupati
  • Publication number: 20040001014
    Abstract: A method and apparatus for generating Gray code for any even count value to enable efficient pointer exchange mechanisms in asynchronous FIFO's. Allowing Gray code for any range of even count values provides the benefit of decreasing metastability when exchanging pointers for FIFO buffers in asynchronous environments. Utilizing the Gray code adjacency principle, which provides that only one bit changes for any successive numbers, in a larger class of numbers than previously utilized, decreases metastability.
    Type: Application
    Filed: June 28, 2002
    Publication date: January 1, 2004
    Inventors: Ashwani Oberai, Kavitha A. Prasad, Sreenath Kurupati
  • Publication number: 20030223415
    Abstract: A method and system is provided for a multi-level memory. The system includes an internal memory and an external memory. Data packets are received through one or more input ports and initially stored in the internal memory. A control unit determines whether there is congestion of resources within the system and transfers data packets to external memory to ease the congestion. Data packets are eventually transferred from the internal or external memory to one or more output ports.
    Type: Application
    Filed: May 29, 2002
    Publication date: December 4, 2003
    Inventors: Rahul Saxena, Hitesh Rastogi, Ashwani Oberai