Patents by Inventor Ashwin Chincholi

Ashwin Chincholi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220103489
    Abstract: Systems, apparatuses, and methods for efficient data transfer in a computing system are disclosed. A source generates packets to send across a communication fabric (or fabric) to a destination. The source generates partition enable signals for the partitions of payload data. The source negates an enable signal for a particular partition when the source determines the packet type indicates the particular partition should have an associated asserted enable signal in the packet, but the source also determines the particular partition includes a particular data pattern. Routing components of the fabric disable clock signals to storage elements assigned to store the particular partition. The destination inserts the particular data pattern for the particular partition in the payload data.
    Type: Application
    Filed: December 10, 2021
    Publication date: March 31, 2022
    Inventors: Greggory D. Donley, Vydhyanathan Kalyanasundharam, Mark A. Silla, Ashwin Chincholi
  • Publication number: 20220103481
    Abstract: Dynamic network-on-chip traffic throttling, including: determining, by a detector module of a network-on-chip, that a predefined condition is met; sending, by the detector module, a signal to a mediator module of the network-on-chip; and sending, in response to the signal, by the mediator module, an indication to a plurality of agents to implement a traffic throttling policy.
    Type: Application
    Filed: September 25, 2020
    Publication date: March 31, 2022
    Inventors: NARENDRA KAMAT, VYDHYANATHAN KALYANASUNDHARAM, GREGG DONLEY, ASHWIN CHINCHOLI
  • Patent number: 11223575
    Abstract: Systems, apparatuses, and methods for efficient data transfer in a computing system are disclosed. A source generates packets to send across a communication fabric (or fabric) to a destination. The source generates partition enable signals for the partitions of payload data. The source negates an enable signal for a particular partition when the source determines the packet type indicates the particular partition should have an associated asserted enable signal in the packet, but the source also determines the particular partition includes a particular data pattern. Routing components of the fabric disable clock signals to storage elements assigned to store the particular partition. The destination inserts the particular data pattern for the particular partition in the payload data.
    Type: Grant
    Filed: December 23, 2019
    Date of Patent: January 11, 2022
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Greggory D. Donley, Vydhyanathan Kalyanasundharam, Mark A. Silla, Ashwin Chincholi
  • Publication number: 20210194827
    Abstract: Systems, apparatuses, and methods for efficient data transfer in a computing system are disclosed. A source generates packets to send across a communication fabric (or fabric) to a destination. The source generates partition enable signals for the partitions of payload data. The source negates an enable signal for a particular partition when the source determines the packet type indicates the particular partition should have an associated asserted enable signal in the packet, but the source also determines the particular partition includes a particular data pattern. Routing components of the fabric disable clock signals to storage elements assigned to store the particular partition. The destination inserts the particular data pattern for the particular partition in the payload data.
    Type: Application
    Filed: December 23, 2019
    Publication date: June 24, 2021
    Inventors: Greggory D. Donley, Vydhyanathan Kalyanasundharam, Mark A. Silla, Ashwin Chincholi
  • Patent number: 10060955
    Abstract: A processing system includes one or more power supply monitors (PSMs) to measure one or more first voltages corresponding to one or more locations in the processing system. The measurements are performed concurrently with the processing system executing one or more code loops. The processing system also includes calibration logic to modify a second voltage provided to the processing system based on a comparison of a reference voltage and the one or more first voltages. The reference voltage is determined based on previous execution of the one or more code loops by the processing system.
    Type: Grant
    Filed: June 25, 2014
    Date of Patent: August 28, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Aaron J. Grenat, Robert A. Hershberger, Sriram Sambamurthy, Samuel D. Naffziger, Christopher E. Tressler, Sho-Chien Kang, Joseph P. Shannon, Krishna Sai Bernucho, Ashwin Chincholi, Michael J. Austin, Steven F. Liepe, Umair B. Cheema
  • Publication number: 20150378411
    Abstract: A processing system includes one or more power supply monitors (PSMs) to measure one or more first voltages corresponding to one or more locations in the processing system. The measurements are performed concurrently with the processing system executing one or more code loops. The processing system also includes calibration logic to modify a second voltage provided to the processing system based on a comparison of a reference voltage and the one or more first voltages. The reference voltage is determined based on previous execution of the one or more code loops by the processing system.
    Type: Application
    Filed: June 25, 2014
    Publication date: December 31, 2015
    Inventors: Aaron J. Grenat, Robert A. Hershberger, Sriram Sambamurthy, Samuel D. Naffziger, Christopher E. Tressler, Sho-Chien Kang, Joseph P. Shannon, Krishna Sai Bernucho, Ashwin Chincholi, Michael J. Austin, Steven F. Liepe, Umair B. Cheema