Abstract: Methods and apparatus are provided for multi-sided storage nodes in three-dimensional memory. An array of vertically stacked memory cells can include horizontally oriented access devices having gates formed horizontally at a different level from each other, channel regions, and first source/drain regions and second source/drain regions separated by the channel regions. The storage nodes include a first electrode, extending in a horizontal direction from, and in electrical contact with, an electrical interface to the second source/drain region of a given one of the vertically stacked memory cells, the first electrode having interior and exterior surfaces, a dielectric material, and a second electrode separated from the interior and exterior surfaces of the first electrode by the dielectric material.

Abstract: An apparatus comprising one or more capacitors that comprise a bottom electrode, a high-k dielectric material, and a top electrode. The bottom electrode comprises an oxygen-doped titanium nitride material and one or more undoped titanium nitride materials. The oxygen-doped titanium nitride material is on sidewalls of the one or more undoped titanium nitride materials and the one or more undoped titanium nitride materials extending between sidewalls of the oxygen-doped titanium nitride material. Electronic devices and methods of forming an electronic device are also disclosed.

Abstract: Methods, apparatuses, and systems related to a three-dimensional semiconductor device having a doped liner at least disposed between a capacitor and an access device. The doped liner may be configured to provide dopants that diffuse into a semiconductor path of the access device and improve an electrical connection between the access device and the capacitor.

Abstract: Methods, systems, and devices for contact foot wet pullback with liner wet punch are described. A first etching operation may be performed on a stack of materials and a first insulative material to form a plurality of segments including contacts, the contacts formed from a first conductive material of the stack of materials and extending at least partially through the first insulative material. A first liner material may be deposited over the segments and the first insulative material, and a directional gas bias operation may be performed to transform a portion of the first liner material in contact with an extension of the contacts into a second liner material. A second etching operation may be performed to remove the second liner material and expose a surface of the extension, and a third etching operation may be performed remove at least a portion of the extension.

Abstract: Some embodiments include an integrated assembly having digit-line-contact-regions between pairs of capacitor-contact-regions. The capacitor-contact-regions are arranged with six adjacent capacitor-contact-regions in a substantially rectangular configuration. Conductive plugs are coupled with the capacitor-contact-regions. Conductive redistribution material is coupled with the conductive plugs. Upper surfaces of the conductive redistribution material are arranged in a substantially hexagonal-close-packed configuration. Digit lines are over the digit-line-contact-regions. Insulative regions are between the digit lines and the conductive plugs. The insulative regions contain voids and/or low-k dielectric material. Capacitors are coupled with the upper surfaces of the conductive redistribution material.

Abstract: Some embodiments include an integrated assembly having digit-line-contact-regions between pairs of capacitor-contact-regions. The capacitor-contact-regions are arranged with six adjacent capacitor-contact-regions in a substantially rectangular configuration. Conductive plugs are coupled with the capacitor-contact-regions. Conductive redistribution material is coupled with the conductive plugs. Upper surfaces of the conductive redistribution material are arranged in a substantially hexagonal-close-packed configuration. Digit lines are over the digit-line-contact-regions. Insulative regions are between the digit lines and the conductive plugs. The insulative regions contain voids and/or low-k dielectric material. Capacitors are coupled with the upper surfaces of the conductive redistribution material.

Abstract: Methods, apparatuses, and systems related to forming a recess in a semiconductor structure are described. An example method includes etching the semiconductor structure using an elevated temperature dilution of acid and water. The method further includes etching the semiconductor structure using a room temperature wet etch of acid and water and a surface modification chemistry.

Abstract: Methods, apparatuses, and systems related to forming a recess in a semiconductor structure are described. An example method includes etching the semiconductor structure using an elevated temperature dilution of acid and water. The method further includes etching the semiconductor structure using a room temperature wet etch of acid and water and a surface modification chemistry.

Abstract: Methods of forming two-dimensional nanopatterns are provided. The method may comprise periodically contacting a vibrating tool comprising a patterned grating edge with a substrate along a first direction in a grating-vibrational indentation patterning process. The patterned grating edge defines a plurality of rows and a plurality of interspersed troughs. The periodic contacting creates a two dimensional array of discontinuous voids in a single-stroke across the surface of the substrate. In other aspects, a microfluidic device for selective arrangement of a microspecies or nanospecies is provided, that includes a substrate comprising a surface defining a two-dimensional pattern of microvoids or nanovoids. In yet other aspects, the present disclosure provides a method for selective arrangement of a microspecies or nanospecies on a substrate.

Abstract: Methods of forming two-dimensional nanopatterns are provided. The method may comprise periodically contacting a vibrating tool comprising a patterned grating edge with a substrate along a first direction in a grating-vibrational indentation patterning process. The patterned grating edge defines a plurality of rows and a plurality of interspersed troughs. The periodic contacting creates a two dimensional array of discontinuous voids in a single-stroke across the surface of the substrate. In other aspects, a microfluidic device for selective arrangement of a microspecies or nanospecies is provided, that includes a substrate comprising a surface defining a two-dimensional pattern of microvoids or nanovoids. In yet other aspects, the present disclosure provides a method for selective arrangement of a microspecies or nanospecies on a substrate.