Patents by Inventor Ashwin Panday

Ashwin Panday has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11563008
    Abstract: Some embodiments include an integrated assembly having digit-line-contact-regions between pairs of capacitor-contact-regions. The capacitor-contact-regions are arranged with six adjacent capacitor-contact-regions in a substantially rectangular configuration. Conductive plugs are coupled with the capacitor-contact-regions. Conductive redistribution material is coupled with the conductive plugs. Upper surfaces of the conductive redistribution material are arranged in a substantially hexagonal-close-packed configuration. Digit lines are over the digit-line-contact-regions. Insulative regions are between the digit lines and the conductive plugs. The insulative regions contain voids and/or low-k dielectric material. Capacitors are coupled with the upper surfaces of the conductive redistribution material.
    Type: Grant
    Filed: March 8, 2021
    Date of Patent: January 24, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Guangjun Yang, Vinay Nair, Devesh Dadhich Shreeram, Ashwin Panday, Kangle Li, Zhiqiang Xie, Silvia Borsari, Mohd Kamran Akhtar, Si-Woo Lee
  • Publication number: 20220285357
    Abstract: Some embodiments include an integrated assembly having digit-line-contact-regions between pairs of capacitor-contact-regions. The capacitor-contact-regions are arranged with six adjacent capacitor-contact-regions in a substantially rectangular configuration. Conductive plugs are coupled with the capacitor-contact-regions. Conductive redistribution material is coupled with the conductive plugs. Upper surfaces of the conductive redistribution material are arranged in a substantially hexagonal-close-packed configuration. Digit lines are over the digit-line-contact-regions. Insulative regions are between the digit lines and the conductive plugs. The insulative regions contain voids and/or low-k dielectric material. Capacitors are coupled with the upper surfaces of the conductive redistribution material.
    Type: Application
    Filed: March 8, 2021
    Publication date: September 8, 2022
    Applicant: Micron Technology, Inc.
    Inventors: Guangjun Yang, Vinay Nair, Devesh Dadhich Shreeram, Ashwin Panday, Kangle Li, Zhiqiang Xie, Silvia Borsari, Mohd Kamran Akhtar, Si-Woo Lee
  • Patent number: 10978306
    Abstract: Methods, apparatuses, and systems related to forming a recess in a semiconductor structure are described. An example method includes etching the semiconductor structure using an elevated temperature dilution of acid and water. The method further includes etching the semiconductor structure using a room temperature wet etch of acid and water and a surface modification chemistry.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: April 13, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Jerome A. Imonigie, Adriel Jebin Jacob Jebaraj, Brian J. Kerley, Sanjeev Sapra, Ashwin Panday
  • Publication number: 20200312954
    Abstract: Methods, apparatuses, and systems related to forming a recess in a semiconductor structure are described. An example method includes etching the semiconductor structure using an elevated temperature dilution of acid and water. The method further includes etching the semiconductor structure using a room temperature wet etch of acid and water and a surface modification chemistry.
    Type: Application
    Filed: March 29, 2019
    Publication date: October 1, 2020
    Inventors: Jerome A. Imonigie, Adriel Jebin Jacob Jebaraj, Brian J. Kerley, Sanjeev Sapra, Ashwin Panday
  • Patent number: 10661273
    Abstract: Methods of forming two-dimensional nanopatterns are provided. The method may comprise periodically contacting a vibrating tool comprising a patterned grating edge with a substrate along a first direction in a grating-vibrational indentation patterning process. The patterned grating edge defines a plurality of rows and a plurality of interspersed troughs. The periodic contacting creates a two dimensional array of discontinuous voids in a single-stroke across the surface of the substrate. In other aspects, a microfluidic device for selective arrangement of a microspecies or nanospecies is provided, that includes a substrate comprising a surface defining a two-dimensional pattern of microvoids or nanovoids. In yet other aspects, the present disclosure provides a method for selective arrangement of a microspecies or nanospecies on a substrate.
    Type: Grant
    Filed: October 13, 2016
    Date of Patent: May 26, 2020
    Assignee: THE REGENTS OF THE UNIVERSITY OF MICHIGAN
    Inventors: Jong G. Ok, Lingjie J. Guo, Long Chen, Ashwin Panday
  • Publication number: 20170100716
    Abstract: Methods of forming two-dimensional nanopatterns are provided. The method may comprise periodically contacting a vibrating tool comprising a patterned grating edge with a substrate along a first direction in a grating-vibrational indentation patterning process. The patterned grating edge defines a plurality of rows and a plurality of interspersed troughs. The periodic contacting creates a two dimensional array of discontinuous voids in a single-stroke across the surface of the substrate. In other aspects, a microfluidic device for selective arrangement of a microspecies or nanospecies is provided, that includes a substrate comprising a surface defining a two-dimensional pattern of microvoids or nanovoids. In yet other aspects, the present disclosure provides a method for selective arrangement of a microspecies or nanospecies on a substrate.
    Type: Application
    Filed: October 13, 2016
    Publication date: April 13, 2017
    Inventors: Jong G. Ok, Lingjie J. Guo, Long Chen, Ashwin Panday