Patents by Inventor Ashwin Ramachandran

Ashwin Ramachandran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12681443
    Abstract: Implementations for receiving an integrated digital twin including multiple digital twins, each digital twin including a computer-executable model of a real-world system used to execute a portion of a process, within the integrated digital twin, a first digital twin providing output to generate input to a second digital twin, receiving enterprise data, the enterprise data being provided from a set of real-world systems used to execute the process, executing, by the integrated digital twin module, simulations of the process using the integrated digital twin and one or more agent-based models based on the enterprise data, at least one agent-based model providing input to the first digital twin, determining simulation results from the simulations, the simulation results including a value of at least one objective function, and adjusting one or more parameters of at least one real-world system used to execute the process based on the simulation results.
    Type: Grant
    Filed: March 24, 2023
    Date of Patent: July 14, 2026
    Assignee: ACCENTURE GLOBAL SOLUTIONS LIMITED
    Inventors: Dnyaneshwar Laxmanrao Ambhore, Saumya Shekhar, Suraj G Jadhav, Ashwin Ramachandran, Ankur Dayal, Hemant Kumar Bansal, Ritdhwara Jain, Vineet Dubey
  • Patent number: 12608550
    Abstract: An Artificial Intelligence (AI) & Generative AI-driven cross-domain document analysis system enables accurate and consistent narratives across a longitudinal timeline for an entity regarding communications in different operational aspects. The document analysis and insight system includes an Artificial Intelligence (AI) powered Search Interface (AIPS) and an Advanced Intelligent Knowledge Engine (AIKE). The AIPS is configured to pre-process documents from structured and unstructured data sources to generate data taxonomies and custom synonym files. The AIKE generates a preliminary evaluation of the various Large Language Models (LLMs) and uses the data taxonomies and custom synonym files to generate prompts that are configured to address limitations of the various LLMs to obtain accurate replies to user requirements.
    Type: Grant
    Filed: March 13, 2024
    Date of Patent: April 21, 2026
    Assignee: ACCENTURE GLOBAL SOLUTIONS LIMITED
    Inventors: Suraj Govind Jadhav, Ashwin Ramachandran, Krishna Kummamuru, Siddharth Dawar, Manoj Shroff
  • Publication number: 20260039328
    Abstract: An example apparatus includes: controller circuitry configured to: instruct transmitter circuitry within a device to perform operations, the transmitter circuitry coupled to a cable interface terminal; responsive to the operations, instruct receiver circuitry within the device to measure a voltage, the receiver circuitry also coupled to the cable interface terminal; and determine, responsive to the measured voltage, when a fault exists on a cable that is coupled to the cable interface terminal.
    Type: Application
    Filed: July 30, 2024
    Publication date: February 5, 2026
    Inventors: Arihant Jain, Ashwin Ramachandran
  • Publication number: 20250364993
    Abstract: An example apparatus includes a first thin-film transistor (TFT) (308P) having a control terminal, a first current terminal, and a second current terminal, the second current terminal of the first TFT (308P) coupled to the supply terminal and the control terminal of the first TFT (308P) coupled to a first bias voltage, a second TFT (312P) having a control terminal, a first current terminal, and a second current terminal, the second current terminal of the second TFT (312P) coupled to the first current terminal of the first TFT (308P), the control terminal of the second TFT (312P) coupled to a second bias voltage, and the first current terminal of the second TFT (312P) coupled to the first output terminal (344), and a first capacitor (309P) coupled between the first input terminal (302) and the control terminal of the first TFT (308P).
    Type: Application
    Filed: May 24, 2024
    Publication date: November 27, 2025
    Inventors: Anirudh Rustagi, Ashwin Ramachandran, Ramsin Ziazadeh
  • Publication number: 20250330207
    Abstract: In an example, a circuit includes a differential input circuit having a first input at a first capacitor terminal and a second input at a second capacitor terminal. The differential input circuit includes a first transistor having a first transistor control terminal and first and second terminals. The differential input circuit includes a second transistor having a second transistor control terminal and first and second terminals, the first terminals of the first and second transistors coupled together. The circuit includes a first capacitor having the first capacitor terminal and having another terminal coupled to the first transistor control terminal. The circuit also includes a second capacitor having the second capacitor terminal and having another terminal coupled to the second transistor control terminal. The circuit includes a first offset correction input coupled to the first transistor control terminal and a second offset correction input coupled to the second transistor control terminal.
    Type: Application
    Filed: June 30, 2025
    Publication date: October 23, 2025
    Inventors: Anindita Borah, Ramsin Ziazadeh, Ashwin Ramachandran
  • Publication number: 20250275531
    Abstract: A semen stabilization medium is described, which includes pH buffer agents, inorganic salts, organic compounds, and amino acids with antioxidant properties. The stabilization medium preserves semen viability for up to 72 hours when the semen is mixed with the stabilization medium and maintained at a temperature within a 20% tolerance of human body temperature.
    Type: Application
    Filed: March 3, 2024
    Publication date: September 4, 2025
    Inventors: Ashwin Ramachandran, Abdul Moiz Syed
  • Publication number: 20250277190
    Abstract: A dual-vial system, kit, and method for preservation of semen samples in mail-in semen analysis kits are described. The system comprises a dual-vial kit that comprises a first vial for collecting a semen sample of a subject, a second vial having a predetermined volume of a stabilization medium, and a transfer device for transferring a predetermined portion of the semen sample from the first vial to the second vial such that the transfer device has a volume allowing transfer of 1 part of the semen sample to be diluted in 3 parts of the stabilization medium in the second vial. Accordingly, the dual-vial kit enables preservation of semen viability for an extended period of up to 72 hours and carrying out of semen analysis within up to 72 hours of storing the semen in the stabilization medium.
    Type: Application
    Filed: March 3, 2024
    Publication date: September 4, 2025
    Inventors: Ashwin Ramachandran, Syed Basim Saroosh Zaidi
  • Publication number: 20250250616
    Abstract: Provided are methods of analyzing target nucleic acids, the methods comprising, using the target nucleic acids as reagents and reporters as substrates, assaying enzyme kinetic parameters of Clustered Regularly Interspaced Short Palindromic Repeats (CRISPR) endonucleases comprising guide RNAs (gRNAs) that hybridize with reference nucleic acids. In certain aspects, certain such methods comprise comparing a sequence of a target nucleic acid with a sequence of a reference nucleic acid. In some embodiments, such comparison is based on the rates of cleavage of the reporters at plurality of concentrations of the reporters. The kinetic parameters can also be the Michaelis-Menten constant (KM), the apparent turnover rate (K*cat), and/or the apparent catalytic efficiency (K*cat/KM). Kits for performing the methods of the disclosure are also provided.
    Type: Application
    Filed: April 12, 2023
    Publication date: August 7, 2025
    Applicant: The Board of Trustees of the Leland Stanford Junior University
    Inventors: Juan Santiago, Alexandre Avaro, Ashwin Ramachandran, Diego Huyke, Charles Blanluet
  • Publication number: 20250224460
    Abstract: A method for detecting a fault with a cable having a resistor divider couple to the cable. The method includes converting a first sense voltage from the resistor divider network to a first digital code, determining whether the first digital code falls within a first range of digital codes corresponding to a first fault associated with the cable, and responsive to determining that the first digital code falls within the first range of digital codes, generating an indication of the first fault.
    Type: Application
    Filed: March 26, 2025
    Publication date: July 10, 2025
    Inventors: Arihant Jain, Ashwin Ramachandran
  • Patent number: 12348256
    Abstract: In an example, a circuit includes a differential input circuit having a first input at a first capacitor terminal and a second input at a second capacitor terminal. The differential input circuit includes a first transistor having a first transistor control terminal and first and second terminals. The differential input circuit includes a second transistor having a second transistor control terminal and first and second terminals, the first terminals of the first and second transistors coupled together. The circuit includes a first capacitor having the first capacitor terminal and having another terminal coupled to the first transistor control terminal. The circuit also includes a second capacitor having the second capacitor terminal and having another terminal coupled to the second transistor control terminal. The circuit includes a first offset correction input coupled to the first transistor control terminal and a second offset correction input coupled to the second transistor control terminal.
    Type: Grant
    Filed: September 29, 2023
    Date of Patent: July 1, 2025
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Anindita Borah, Ramsin Ziazadeh, Ashwin Ramachandran
  • Publication number: 20250148209
    Abstract: An Artificial Intelligence (AI) & Generative AI-driven cross-domain document analysis system enables accurate and consistent narratives across a longitudinal timeline for an entity regarding communications in different operational aspects. The document analysis and insight system includes an Artificial Intelligence (AI) powered Search Interface (AIPS) and an Advanced Intelligent Knowledge Engine (AIKE). The AIPS is configured to pre-process documents from structured and unstructured data sources to generate data taxonomies and custom synonym files. The AIKE generates a preliminary evaluation of the various Large Language Models (LLMs) and uses the data taxonomies and custom synonym files to generate prompts that are configured to address limitations of the various LLMs to obtain accurate replies to user requirements.
    Type: Application
    Filed: March 13, 2024
    Publication date: May 8, 2025
    Applicant: ACCENTURE GLOBAL SOLUTIONS LIMITED
    Inventors: Suraj Govind JADHAV, Ashwin RAMACHANDRAN, Krishna KUMMAMURU, Siddharth DAWAR, Manoj SHROFF
  • Patent number: 12287377
    Abstract: A method for detecting a fault with a cable having a resistor divider couple to the cable. The method includes converting a first sense voltage from the resistor divider network to a first digital code, determining whether the first digital code falls within a first range of digital codes corresponding to a first fault associated with the cable, and responsive to determining that the first digital code falls within the first range of digital codes, generating an indication of the first fault.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: April 29, 2025
    Assignee: Texas Instruments Incorporated
    Inventors: Arihant Jain, Ashwin Ramachandran
  • Publication number: 20250112661
    Abstract: In an example, a circuit includes a differential input circuit having a first input at a first capacitor terminal and a second input at a second capacitor terminal. The differential input circuit includes a first transistor having a first transistor control terminal and first and second terminals. The differential input circuit includes a second transistor having a second transistor control terminal and first and second terminals, the first terminals of the first and second transistors coupled together. The circuit includes a first capacitor having the first capacitor terminal and having another terminal coupled to the first transistor control terminal. The circuit also includes a second capacitor having the second capacitor terminal and having another terminal coupled to the second transistor control terminal. The circuit includes a first offset correction input coupled to the first transistor control terminal and a second offset correction input coupled to the second transistor control terminal.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Inventors: Anindita BORAH, Ramsin ZIAZADEH, Ashwin RAMACHANDRAN
  • Publication number: 20250023558
    Abstract: An example apparatus includes: a capacitor having a terminal; comparator circuitry having an input terminal and an output terminal, the input terminal of the comparator circuitry coupled to the terminal of the capacitor; timer circuitry having an input terminal and an output terminal, the input terminal of the timer circuitry coupled to the output terminal of the comparator circuitry; and configuration determination circuitry having an input and an output, the input of the configuration determination circuitry coupled to the output of the timer circuitry; and a configuration register having an input coupled to the output of the configuration determination circuitry.
    Type: Application
    Filed: January 31, 2024
    Publication date: January 16, 2025
    Inventors: Win N Maung, Richard Edwin Hubbard, Jonathan Lee Valdez, Mark Edward Wentroble, Justin Silver, Anirudh Rustagi, Ashwin Ramachandran
  • Publication number: 20240319687
    Abstract: Implementations for receiving an integrated digital twin including multiple digital twins, each digital twin including a computer-executable model of a real-world system used to execute a portion of a process, within the integrated digital twin, a first digital twin providing output to generate input to a second digital twin, receiving enterprise data, the enterprise data being provided from a set of real-world systems used to execute the process, executing, by the integrated digital twin module, simulations of the process using the integrated digital twin and one or more agent-based models based on the enterprise data, at least one agent-based model providing input to the first digital twin, determining simulation results from the simulations, the simulation results including a value of at least one objective function, and adjusting one or more parameters of at least one real-world system used to execute the process based on the simulation results.
    Type: Application
    Filed: March 24, 2023
    Publication date: September 26, 2024
    Inventors: Dnyaneshwar Laxmanrao Ambhore, Saumya Shekhar, Suraj G Jadhav, Ashwin Ramachandran, Ankur Dayal, Hemant Kumar Bansal, Ritdhwara Jain, Vineet Dubey
  • Publication number: 20230288495
    Abstract: A method for detecting a fault with a cable having a resistor divider couple to the cable. The method includes converting a first sense voltage from the resistor divider network to a first digital code, determining whether the first digital code falls within a first range of digital codes corresponding to a first fault associated with the cable, and responsive to determining that the first digital code falls within the first range of digital codes, generating an indication of the first fault.
    Type: Application
    Filed: March 11, 2022
    Publication date: September 14, 2023
    Inventors: Arihant JAIN, Ashwin RAMACHANDRAN
  • Patent number: 11283408
    Abstract: Described examples include Ethernet physical layer (PHY) interface integrated circuits with transmit interface circuitry for transmitting data to an Ethernet network through a magnetic interface, which includes a voltage mode first amplifier with an output that generates a first voltage signal from a supply voltage according to a data input signal. The transmit interface circuit also includes a feedforward second amplifier circuit with an output stage that operates in a first mode to generate a current signal from the supply voltage according to the first voltage signal and to provide the current signal to the first amplifier output to boost a peak voltage at the output above the supply voltage to facilitate support for higher peak signal voltage swings for 10Base-T applications while using 2.5 volt or other low voltage supply levels.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: March 22, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sumantra Seth, Ashwin Ramachandran, Gururaj Ghorpade
  • Patent number: 10875792
    Abstract: The present disclosure relates to a capacitive deionization (CDI) system for desalinating salt water. The system may have a capacitor formed by spaced apart first and second electrodes, which enable a fluid flow containing salt water to pass either between them or through them. An input electrical power source is configured to generate an electrical forcing signal between the two electrodes. The electrical forcing signal represents a periodic signal including at least one of voltage or current, and which can be represented as a Fourier series. One component of the Fourier series is a constant, and a second component of the Fourier series is a sinusoidal wave of non-zero frequency which has the highest amplitude of the additive components of the Fourier series. The amplitude of the sinusoidal wave component is between 0.85 and 1.25 times the amplitude of the periodic signal.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: December 29, 2020
    Assignee: Lawrence Livermore National Security, LLC
    Inventors: Steven Hawks, Michael Stadermann, Juan G. Santiago, Ashwin Ramachandran
  • Publication number: 20190359506
    Abstract: The present disclosure relates to a capacitive deionization (CDI) system for desalinating salt water. The system may have a capacitor formed by spaced apart first and second electrodes, which enable a fluid flow containing salt water to pass either between them or through them. An input electrical power source is configured to generate an electrical forcing signal between the two electrodes. The electrical forcing signal represents a periodic signal including at least one of voltage or current, and which can be represented as a Fourier series. One component of the Fourier series is a constant, and a second component of the Fourier series is a sinusoidal wave of non-zero frequency which has the highest amplitude of the additive components of the Fourier series. The amplitude of the sinusoidal wave component is between 0.85 and 1.25 times the amplitude of the periodic signal.
    Type: Application
    Filed: May 21, 2019
    Publication date: November 28, 2019
    Inventors: Steven HAWKS, Michael STADERMANN, Juan G. SANTIAGO, Ashwin RAMACHANDRAN
  • Patent number: 10386242
    Abstract: The disclosure provides a circuit that includes an analog control block, and a plurality of temperature sensors coupled to the analog control block. At least one temperature sensor of the plurality of temperature sensors includes a first transistor coupled to a first current source. A second transistor is coupled to a second current source and to the first transistor. The analog control block measures a local temperature from a first potential generated across the first transistor and from a second potential generated across the second transistor.
    Type: Grant
    Filed: September 21, 2015
    Date of Patent: August 20, 2019
    Assignee: Texas Instruments Incorporated
    Inventor: Ashwin Ramachandran