Patents by Inventor Ashwin Ramachandran
Ashwin Ramachandran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12681443Abstract: Implementations for receiving an integrated digital twin including multiple digital twins, each digital twin including a computer-executable model of a real-world system used to execute a portion of a process, within the integrated digital twin, a first digital twin providing output to generate input to a second digital twin, receiving enterprise data, the enterprise data being provided from a set of real-world systems used to execute the process, executing, by the integrated digital twin module, simulations of the process using the integrated digital twin and one or more agent-based models based on the enterprise data, at least one agent-based model providing input to the first digital twin, determining simulation results from the simulations, the simulation results including a value of at least one objective function, and adjusting one or more parameters of at least one real-world system used to execute the process based on the simulation results.Type: GrantFiled: March 24, 2023Date of Patent: July 14, 2026Assignee: ACCENTURE GLOBAL SOLUTIONS LIMITEDInventors: Dnyaneshwar Laxmanrao Ambhore, Saumya Shekhar, Suraj G Jadhav, Ashwin Ramachandran, Ankur Dayal, Hemant Kumar Bansal, Ritdhwara Jain, Vineet Dubey
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Patent number: 12608550Abstract: An Artificial Intelligence (AI) & Generative AI-driven cross-domain document analysis system enables accurate and consistent narratives across a longitudinal timeline for an entity regarding communications in different operational aspects. The document analysis and insight system includes an Artificial Intelligence (AI) powered Search Interface (AIPS) and an Advanced Intelligent Knowledge Engine (AIKE). The AIPS is configured to pre-process documents from structured and unstructured data sources to generate data taxonomies and custom synonym files. The AIKE generates a preliminary evaluation of the various Large Language Models (LLMs) and uses the data taxonomies and custom synonym files to generate prompts that are configured to address limitations of the various LLMs to obtain accurate replies to user requirements.Type: GrantFiled: March 13, 2024Date of Patent: April 21, 2026Assignee: ACCENTURE GLOBAL SOLUTIONS LIMITEDInventors: Suraj Govind Jadhav, Ashwin Ramachandran, Krishna Kummamuru, Siddharth Dawar, Manoj Shroff
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Publication number: 20260039328Abstract: An example apparatus includes: controller circuitry configured to: instruct transmitter circuitry within a device to perform operations, the transmitter circuitry coupled to a cable interface terminal; responsive to the operations, instruct receiver circuitry within the device to measure a voltage, the receiver circuitry also coupled to the cable interface terminal; and determine, responsive to the measured voltage, when a fault exists on a cable that is coupled to the cable interface terminal.Type: ApplicationFiled: July 30, 2024Publication date: February 5, 2026Inventors: Arihant Jain, Ashwin Ramachandran
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Publication number: 20250364993Abstract: An example apparatus includes a first thin-film transistor (TFT) (308P) having a control terminal, a first current terminal, and a second current terminal, the second current terminal of the first TFT (308P) coupled to the supply terminal and the control terminal of the first TFT (308P) coupled to a first bias voltage, a second TFT (312P) having a control terminal, a first current terminal, and a second current terminal, the second current terminal of the second TFT (312P) coupled to the first current terminal of the first TFT (308P), the control terminal of the second TFT (312P) coupled to a second bias voltage, and the first current terminal of the second TFT (312P) coupled to the first output terminal (344), and a first capacitor (309P) coupled between the first input terminal (302) and the control terminal of the first TFT (308P).Type: ApplicationFiled: May 24, 2024Publication date: November 27, 2025Inventors: Anirudh Rustagi, Ashwin Ramachandran, Ramsin Ziazadeh
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Publication number: 20250330207Abstract: In an example, a circuit includes a differential input circuit having a first input at a first capacitor terminal and a second input at a second capacitor terminal. The differential input circuit includes a first transistor having a first transistor control terminal and first and second terminals. The differential input circuit includes a second transistor having a second transistor control terminal and first and second terminals, the first terminals of the first and second transistors coupled together. The circuit includes a first capacitor having the first capacitor terminal and having another terminal coupled to the first transistor control terminal. The circuit also includes a second capacitor having the second capacitor terminal and having another terminal coupled to the second transistor control terminal. The circuit includes a first offset correction input coupled to the first transistor control terminal and a second offset correction input coupled to the second transistor control terminal.Type: ApplicationFiled: June 30, 2025Publication date: October 23, 2025Inventors: Anindita Borah, Ramsin Ziazadeh, Ashwin Ramachandran
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Publication number: 20250275531Abstract: A semen stabilization medium is described, which includes pH buffer agents, inorganic salts, organic compounds, and amino acids with antioxidant properties. The stabilization medium preserves semen viability for up to 72 hours when the semen is mixed with the stabilization medium and maintained at a temperature within a 20% tolerance of human body temperature.Type: ApplicationFiled: March 3, 2024Publication date: September 4, 2025Inventors: Ashwin Ramachandran, Abdul Moiz Syed
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Publication number: 20250277190Abstract: A dual-vial system, kit, and method for preservation of semen samples in mail-in semen analysis kits are described. The system comprises a dual-vial kit that comprises a first vial for collecting a semen sample of a subject, a second vial having a predetermined volume of a stabilization medium, and a transfer device for transferring a predetermined portion of the semen sample from the first vial to the second vial such that the transfer device has a volume allowing transfer of 1 part of the semen sample to be diluted in 3 parts of the stabilization medium in the second vial. Accordingly, the dual-vial kit enables preservation of semen viability for an extended period of up to 72 hours and carrying out of semen analysis within up to 72 hours of storing the semen in the stabilization medium.Type: ApplicationFiled: March 3, 2024Publication date: September 4, 2025Inventors: Ashwin Ramachandran, Syed Basim Saroosh Zaidi
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Publication number: 20250250616Abstract: Provided are methods of analyzing target nucleic acids, the methods comprising, using the target nucleic acids as reagents and reporters as substrates, assaying enzyme kinetic parameters of Clustered Regularly Interspaced Short Palindromic Repeats (CRISPR) endonucleases comprising guide RNAs (gRNAs) that hybridize with reference nucleic acids. In certain aspects, certain such methods comprise comparing a sequence of a target nucleic acid with a sequence of a reference nucleic acid. In some embodiments, such comparison is based on the rates of cleavage of the reporters at plurality of concentrations of the reporters. The kinetic parameters can also be the Michaelis-Menten constant (KM), the apparent turnover rate (K*cat), and/or the apparent catalytic efficiency (K*cat/KM). Kits for performing the methods of the disclosure are also provided.Type: ApplicationFiled: April 12, 2023Publication date: August 7, 2025Applicant: The Board of Trustees of the Leland Stanford Junior UniversityInventors: Juan Santiago, Alexandre Avaro, Ashwin Ramachandran, Diego Huyke, Charles Blanluet
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Publication number: 20250224460Abstract: A method for detecting a fault with a cable having a resistor divider couple to the cable. The method includes converting a first sense voltage from the resistor divider network to a first digital code, determining whether the first digital code falls within a first range of digital codes corresponding to a first fault associated with the cable, and responsive to determining that the first digital code falls within the first range of digital codes, generating an indication of the first fault.Type: ApplicationFiled: March 26, 2025Publication date: July 10, 2025Inventors: Arihant Jain, Ashwin Ramachandran
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Patent number: 12348256Abstract: In an example, a circuit includes a differential input circuit having a first input at a first capacitor terminal and a second input at a second capacitor terminal. The differential input circuit includes a first transistor having a first transistor control terminal and first and second terminals. The differential input circuit includes a second transistor having a second transistor control terminal and first and second terminals, the first terminals of the first and second transistors coupled together. The circuit includes a first capacitor having the first capacitor terminal and having another terminal coupled to the first transistor control terminal. The circuit also includes a second capacitor having the second capacitor terminal and having another terminal coupled to the second transistor control terminal. The circuit includes a first offset correction input coupled to the first transistor control terminal and a second offset correction input coupled to the second transistor control terminal.Type: GrantFiled: September 29, 2023Date of Patent: July 1, 2025Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Anindita Borah, Ramsin Ziazadeh, Ashwin Ramachandran
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Publication number: 20250148209Abstract: An Artificial Intelligence (AI) & Generative AI-driven cross-domain document analysis system enables accurate and consistent narratives across a longitudinal timeline for an entity regarding communications in different operational aspects. The document analysis and insight system includes an Artificial Intelligence (AI) powered Search Interface (AIPS) and an Advanced Intelligent Knowledge Engine (AIKE). The AIPS is configured to pre-process documents from structured and unstructured data sources to generate data taxonomies and custom synonym files. The AIKE generates a preliminary evaluation of the various Large Language Models (LLMs) and uses the data taxonomies and custom synonym files to generate prompts that are configured to address limitations of the various LLMs to obtain accurate replies to user requirements.Type: ApplicationFiled: March 13, 2024Publication date: May 8, 2025Applicant: ACCENTURE GLOBAL SOLUTIONS LIMITEDInventors: Suraj Govind JADHAV, Ashwin RAMACHANDRAN, Krishna KUMMAMURU, Siddharth DAWAR, Manoj SHROFF
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Patent number: 12287377Abstract: A method for detecting a fault with a cable having a resistor divider couple to the cable. The method includes converting a first sense voltage from the resistor divider network to a first digital code, determining whether the first digital code falls within a first range of digital codes corresponding to a first fault associated with the cable, and responsive to determining that the first digital code falls within the first range of digital codes, generating an indication of the first fault.Type: GrantFiled: March 11, 2022Date of Patent: April 29, 2025Assignee: Texas Instruments IncorporatedInventors: Arihant Jain, Ashwin Ramachandran
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Publication number: 20250112661Abstract: In an example, a circuit includes a differential input circuit having a first input at a first capacitor terminal and a second input at a second capacitor terminal. The differential input circuit includes a first transistor having a first transistor control terminal and first and second terminals. The differential input circuit includes a second transistor having a second transistor control terminal and first and second terminals, the first terminals of the first and second transistors coupled together. The circuit includes a first capacitor having the first capacitor terminal and having another terminal coupled to the first transistor control terminal. The circuit also includes a second capacitor having the second capacitor terminal and having another terminal coupled to the second transistor control terminal. The circuit includes a first offset correction input coupled to the first transistor control terminal and a second offset correction input coupled to the second transistor control terminal.Type: ApplicationFiled: September 29, 2023Publication date: April 3, 2025Inventors: Anindita BORAH, Ramsin ZIAZADEH, Ashwin RAMACHANDRAN
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Publication number: 20250023558Abstract: An example apparatus includes: a capacitor having a terminal; comparator circuitry having an input terminal and an output terminal, the input terminal of the comparator circuitry coupled to the terminal of the capacitor; timer circuitry having an input terminal and an output terminal, the input terminal of the timer circuitry coupled to the output terminal of the comparator circuitry; and configuration determination circuitry having an input and an output, the input of the configuration determination circuitry coupled to the output of the timer circuitry; and a configuration register having an input coupled to the output of the configuration determination circuitry.Type: ApplicationFiled: January 31, 2024Publication date: January 16, 2025Inventors: Win N Maung, Richard Edwin Hubbard, Jonathan Lee Valdez, Mark Edward Wentroble, Justin Silver, Anirudh Rustagi, Ashwin Ramachandran
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Publication number: 20240319687Abstract: Implementations for receiving an integrated digital twin including multiple digital twins, each digital twin including a computer-executable model of a real-world system used to execute a portion of a process, within the integrated digital twin, a first digital twin providing output to generate input to a second digital twin, receiving enterprise data, the enterprise data being provided from a set of real-world systems used to execute the process, executing, by the integrated digital twin module, simulations of the process using the integrated digital twin and one or more agent-based models based on the enterprise data, at least one agent-based model providing input to the first digital twin, determining simulation results from the simulations, the simulation results including a value of at least one objective function, and adjusting one or more parameters of at least one real-world system used to execute the process based on the simulation results.Type: ApplicationFiled: March 24, 2023Publication date: September 26, 2024Inventors: Dnyaneshwar Laxmanrao Ambhore, Saumya Shekhar, Suraj G Jadhav, Ashwin Ramachandran, Ankur Dayal, Hemant Kumar Bansal, Ritdhwara Jain, Vineet Dubey
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Publication number: 20230288495Abstract: A method for detecting a fault with a cable having a resistor divider couple to the cable. The method includes converting a first sense voltage from the resistor divider network to a first digital code, determining whether the first digital code falls within a first range of digital codes corresponding to a first fault associated with the cable, and responsive to determining that the first digital code falls within the first range of digital codes, generating an indication of the first fault.Type: ApplicationFiled: March 11, 2022Publication date: September 14, 2023Inventors: Arihant JAIN, Ashwin RAMACHANDRAN
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Patent number: 11283408Abstract: Described examples include Ethernet physical layer (PHY) interface integrated circuits with transmit interface circuitry for transmitting data to an Ethernet network through a magnetic interface, which includes a voltage mode first amplifier with an output that generates a first voltage signal from a supply voltage according to a data input signal. The transmit interface circuit also includes a feedforward second amplifier circuit with an output stage that operates in a first mode to generate a current signal from the supply voltage according to the first voltage signal and to provide the current signal to the first amplifier output to boost a peak voltage at the output above the supply voltage to facilitate support for higher peak signal voltage swings for 10Base-T applications while using 2.5 volt or other low voltage supply levels.Type: GrantFiled: December 19, 2018Date of Patent: March 22, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sumantra Seth, Ashwin Ramachandran, Gururaj Ghorpade
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Patent number: 10875792Abstract: The present disclosure relates to a capacitive deionization (CDI) system for desalinating salt water. The system may have a capacitor formed by spaced apart first and second electrodes, which enable a fluid flow containing salt water to pass either between them or through them. An input electrical power source is configured to generate an electrical forcing signal between the two electrodes. The electrical forcing signal represents a periodic signal including at least one of voltage or current, and which can be represented as a Fourier series. One component of the Fourier series is a constant, and a second component of the Fourier series is a sinusoidal wave of non-zero frequency which has the highest amplitude of the additive components of the Fourier series. The amplitude of the sinusoidal wave component is between 0.85 and 1.25 times the amplitude of the periodic signal.Type: GrantFiled: May 21, 2019Date of Patent: December 29, 2020Assignee: Lawrence Livermore National Security, LLCInventors: Steven Hawks, Michael Stadermann, Juan G. Santiago, Ashwin Ramachandran
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Publication number: 20190359506Abstract: The present disclosure relates to a capacitive deionization (CDI) system for desalinating salt water. The system may have a capacitor formed by spaced apart first and second electrodes, which enable a fluid flow containing salt water to pass either between them or through them. An input electrical power source is configured to generate an electrical forcing signal between the two electrodes. The electrical forcing signal represents a periodic signal including at least one of voltage or current, and which can be represented as a Fourier series. One component of the Fourier series is a constant, and a second component of the Fourier series is a sinusoidal wave of non-zero frequency which has the highest amplitude of the additive components of the Fourier series. The amplitude of the sinusoidal wave component is between 0.85 and 1.25 times the amplitude of the periodic signal.Type: ApplicationFiled: May 21, 2019Publication date: November 28, 2019Inventors: Steven HAWKS, Michael STADERMANN, Juan G. SANTIAGO, Ashwin RAMACHANDRAN
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Patent number: 10386242Abstract: The disclosure provides a circuit that includes an analog control block, and a plurality of temperature sensors coupled to the analog control block. At least one temperature sensor of the plurality of temperature sensors includes a first transistor coupled to a first current source. A second transistor is coupled to a second current source and to the first transistor. The analog control block measures a local temperature from a first potential generated across the first transistor and from a second potential generated across the second transistor.Type: GrantFiled: September 21, 2015Date of Patent: August 20, 2019Assignee: Texas Instruments IncorporatedInventor: Ashwin Ramachandran