Abstract: Embodiments relate to an image signal processor that includes an image processing circuit, a buffer, and a rate limiter circuit. The image processing circuit perform operations associated with image signal processing. The buffer stores the image data provided by the system memory. The buffer includes a shared that is dynamically allocated among the image processing circuits. The rate limiter circuit arbitrates allocation of the shared section. The arbitration process includes allocating data credits for the shared section to an image processing circuit. The rate limiter circuit determines a first number of blocks in the shared section that are allocated for pending requests and a second number of blocks that include data pending to be consumed by the image processing circuit. If the total allocated blocks occupied by the image processing circuit exceed a throttling threshold, the image processing circuit will be throttled by an exponential factor.