Abstract: A system and method for accelerating the execution of applications in computing environments. The method includes receiving a request for execution of a plug-in of a computing application and analyzing a network for accelerators for executing the plug-in. The method further includes identifying a designated accelerator residing on a device that is remote from the application and executing the plug-in with the designated accelerator.

Abstract: A structure and method comprises a data structure representing a characteristic of an object in the virtual interactive environment. The device further comprises a client simulator to perform a first simulation of the characteristic of the object in the virtual interactive environment and a server simulator to perform a second simulation of the characteristic of the object in the virtual interactive environment. The device further comprises a synchronizer to synchronize the first and the second simulations.

Abstract: A system including a south bridge, a first processor connected to the south bridge, and a second processor connected to the south bridge. The system further includes at least one device connected to the south bridge, and a resource manager coupled to the south bridge that allocates use of the at least one device between the first processor and the second processor.

Abstract: A system and method for accelerating the execution of applications in computing environments. The method includes receiving a request for execution of a plug-in of a computing application and analyzing a network for accelerators for executing the plug-in. The method further includes identifying a designated accelerator residing on a device that is remote from the application and executing the plug-in with the designated accelerator.

Abstract: A structure and method comprises a data structure representing a characteristic of an object in the virtual interactive environment. The device further comprises a client simulator to perform a first simulation of the characteristic of the object in the virtual interactive environment and a server simulator to perform a second simulation of the characteristic of the object in the virtual interactive environment. The device further comprises a synchronizer to synchronize the first and the second simulations.

Abstract: A device comprises two or more nodes for processing a simulation of a virtual interactive environment. The two or more nodes comprising at least one component to determine workload amongst at least a first node and a second node the two or more nodes. The at least one component further delegates work to the second node when the workload on the first node exceeds a predetermined boundary, and accepts work from the second node when the workload on the second node is within the predetermined boundary.

Abstract: A system including a south bridge, a first processor connected to the south bridge, and a second processor connected to the south bridge. The system further includes at least one device connected to the south bridge, and a resource manager coupled to the south bridge that allocates use of the at least one device between the first processor and the second processor.

Abstract: A microprocessor (10) comprising a central processor unit core (12) operable to write information during a write cycle and a cache circuit (18) coupled to the central processor unit core and operable to evict information. The microprocessor further includes a combined storage queue (16) coupled to the central processor unit core and to the cache circuit. The combined storage queue includes a set of logical storage blocks (22c) which is operable to store both information written by the central processor unit core and information evicted by the cache circuit. Other circuits, systems, and methods are also disclosed and claimed.

Abstract: A microprocessor-based system (2) is disclosed, based on an x86-architecture microprocessor (5). The system includes a memory address space (30) and a input/output address space (40), where input/output operations are performed in an I/O mapped manner. According to a first embodiment of the invention, burstable access is performed to areas of the main memory (32) which are blocked from cache access, by the microprocessor (5) asserting the cache request signal (CACHE#) in combination with the control signal (M/IO#) indicating that an I/O operation is requested. The memory controller (10) interprets this combination as a burst request to the non-cacheable memory location (32), indicates the grant of burst access by asserting the cache acknowledge control signal (KEN#), and the burst memory access is then effected.

Abstract: A microprocessor comprising an instruction pipeline (36) comprising a plurality of successive instruction stages. An instruction passes from a beginning stage (38), through a plurality of intermediary stages (40 through 52), and to an ending stage (54) of the plurality of successive instruction stages. The microprocessor also comprises a storage circuit (58) coupled to receive program thread information output from a first stage (48) of the intermediary stages. Still further, the microprocessor comprises selection circuitry (56) comprising a first input, a second input, and an output for outputting output information from its first and second inputs. The first input of the selection circuitry is coupled to receive output information output from the first stage. The second input of the selection circuitry is coupled to receive program thread information output from the storage circuit.