Abstract: A ripple voltage detector circuit comprises a pulse generator, a direct current-to-direct current (DC-DC) converter coupled to the pulse generator, and a first control loop coupled to the pulse generator and the DC-DC converter. The first control loop is configured to measure an output voltage of the DC-DC converter, determine an output ripple voltage of the output voltage, determine a ripple coefficient based on the output ripple voltage, determine a reference peak inductor current based on the ripple coefficient, and determine a peak value of an inductor current during a switching cycle, and transition a switching state of the DC-DC converter based on the reference peak inductor current and the peak value of the inductor current.

Abstract: A ripple voltage detector circuit comprises a pulse generator, a direct current-to-direct current (DC-DC) converter coupled to the pulse generator, and a first control loop coupled to the pulse generator and the DC-DC converter. The first control loop is configured to measure an output voltage of the DC-DC converter, determine an output ripple voltage of the output voltage, determine a ripple coefficient based on the output ripple voltage, determine a reference peak inductor current based on the ripple coefficient, and determine a peak value of an inductor current during a switching cycle, and transition a switching state of the DC-DC converter based on the reference peak inductor current and the peak value of the inductor current.

Abstract: A system includes a digital controller in a voltage regulator. The system also includes a passgate array including two or more passgate transistors, where the passgate array is configured to provide a load current to a load, and where the digital controller is configured to activate and deactivate each passgate transistor in the passgate array. The system also includes a feedback loop configured to provide an error signal to the digital controller, the error signal based on a difference between an output voltage of the voltage regulator and a programmed voltage for the voltage regulator. The digital controller is configured to activate or deactivate a passgate transistor based at least in part on the error signal. The digital controller is also configured to activate at least one passgate transistor and deactivate at least one passgate transistor responsive to a clock cycle.

Abstract: In described examples, a first and second driver each include a first-rail output transistor including a first terminal coupled to a first power rail and a second-rail output transistor including a first terminal coupled to a second power rail. The first-rail output transistor of each of the first and second drivers includes a second terminal coupled to a second terminal of the second-rail output transistor of an output node of each respective first and second driver. A resistive load includes a first terminal coupled to the first-driver output node and includes a second terminal coupled to the second-driver output node. A sampling circuit generates an indication of an impedance of at least one of the output transistors of the first and second drivers.

Abstract: A proportional to absolute temperature (PTAT) generator, for example, generates a PTAT current (IPTAT) and a VBE (voltage base-to-emitter) in a first regulation loop. A voltage-to-current converter is operable to generate a complementary to absolute temperature current (ICTAT). The IPTAT and ICTAT are summed to obtain a zero temperature coefficient current (IZTC). One ICTAT and one resistor are used to generate the IZTC signal.

Abstract: In described examples, a first and second driver each include a first-rail output transistor including a first terminal coupled to a first power rail and a second-rail output transistor including a first terminal coupled to a second power rail. The first-rail output transistor of each of the first and second drivers includes a second terminal coupled to a second terminal of the second-rail output transistor of an output node of each respective first and second driver. A resistive load includes a first terminal coupled to the first-driver output node and includes a second terminal coupled to the second-driver output node. A sampling circuit generates an indication of an impedance of at least one of the output transistors of the first and second drivers.

Abstract: A proportional to absolute temperature (PTAT) generator generates a current PTAT (IPTAT) and a fractional VBE in a first regulation loop. A level shifting voltage-to-current converter is arranged as a second regulation loop and is operable to generate a current ZTC (IZTC) and/or a voltage ZTC (VZTC). Both regulation loops are nested into each other. In an embodiment, the voltage-to-current converter is operable to sum a scaled voltage PTAT (VPTAT/Y) with the fractional VBE (VBE/X) to generate the ZTC signal. In another embodiment, the voltage-to-current converter is operable to sum a delta voltage threshold (?VTH) with the fractional VBE (VBE/X) to generate the ZTC signal.

Abstract: A start-up circuit for a reference circuit such as a bandgap reference circuit. The start-up circuit includes a diode-connected metal-oxide-semiconductor (MOS) transistor connected between a power supply node and a start-up node that is connected in turn to the gate of a current control MOS transistor in the reference circuit. The diode-connected MOS transistor and the current control MOS transistor are matched with one another. To start up the reference circuit, current is conducted through the diode-connected MOS transistor to set the gate voltage of the current control transistor at a threshold voltage below the power supply voltage. Current conducted by the current control transistor initiates operation of the bandgap reference circuit, and disables the start-up circuit.

Abstract: A proportional to absolute temperature (PTAT) generator, for example, generates a PTAT current (IPTAT) and a VBE (voltage base-to-emitter) in a first regulation loop. A voltage-to-current converter is operable to generate a complementary to absolute temperature current (ICTAT). The IPTAT and ICTAT are summed to obtain a zero temperature coefficient current (IZTC). One ICTAT and one resistor are used to generate the IZTC signal.

Abstract: A proportional to absolute temperature (PTAT) generator generates a current PTAT (IPTAT) and a fractional VBE in a first regulation loop. A level shifting voltage-to-current converter is arranged as a second regulation loop and is operable to generate a current ZTC (IZTC) and/or a voltage ZTC (VZTC). Both regulation loops are nested into each other. In an embodiment, the voltage-to-current converter is operable to sum a scaled voltage PTAT (VPTAT/Y) with the fractional VBE (VBE/X) to generate the ZTC signal. In another embodiment, the voltage-to-current converter is operable to sum a delta voltage threshold (?VTH) with the fractional VBE (VBE/X) to generate the ZTC signal.

Abstract: A start-up circuit for a reference circuit such as a bandgap reference circuit. The start-up circuit includes a diode-connected metal-oxide-semiconductor (MOS) transistor connected between a power supply node and a start-up node that is connected in turn to the gate of a current control MOS transistor in the reference circuit. The diode-connected MOS transistor and the current control MOS transistor are matched with one another. To start up the reference circuit, current is conducted through the diode-connected MOS transistor to set the gate voltage of the current control transistor at a threshold voltage below the power supply voltage. Current conducted by the current control transistor initiates operation of the bandgap reference circuit, and disables the start-up circuit.

Abstract: A bandgap reference circuit with curvature compensation. The circuit includes a first current mirror that mirrors the current conducted by the bandgap reference. A difference between the gate-to-source voltages in the two legs provides a first mirrored current with non-linear temperature stability. This first mirrored current is again mirrored by a second current mirror in which the mirror transistors also have differing gate-to-source voltages, with the current from this second current mirror coupled to the bandgap reference to compensate for curvature in the CTAT current over temperature.

Abstract: A dual-comparator circuit includes a main comparator providing a first decision output (outmain) including a main MOS differential pair, and an auxiliary comparator including an auxiliary MOS differential pair providing a second decision output (outaux). The auxiliary comparator receives a differential input voltage (Vin), and generates a control signal that is coupled to an enable input of the main comparator. A first operating mode (OM) is implemented when |Vin|<a predetermined voltage level (PVL), where the control signal activates the main comparator. A second OM is implemented when |Vin|?PVL where the main differential pair is protected by a switch from developing transient voltage input offset (VIO). Logic circuitry has logic inputs receiving outaux and outmain, and a logic output providing a decision result for the dual-comparator circuit using outmain when in the first OM and outaux when in the second OM.

Abstract: A bandgap reference (BGR) startup verification circuit includes a current minor for receiving an output current from a bandgap reference (BGR) circuit and generating output currents therefrom. A first verification sub-circuit is coupled to receive a first output current to generate a detection voltage (Vdet) and includes a voltage comparator receiving Vdet and a voltage output of the BGR circuit (VBG) to provide a first verification output. A second verification sub-circuit including a voltage comparator is coupled to receive a second output current and a second reference current and provide a second verification output. A third verification sub-circuit includes a current comparator coupled to receive a third output current and a third reference current and provide a third verification output. A digital state machine has inputs receiving the first, second and third verification output, and circuitry for processing these outputs to determine whether the BGR circuit has properly started.

Abstract: A dual-comparator circuit includes a main comparator providing a first decision output (outmain) including a main MOS differential pair, and an auxiliary comparator including an auxiliary MOS differential pair providing a second decision output (outaux). The auxiliary comparator receives a differential input voltage (Vin), and generates a control signal that is coupled to an enable input of the main comparator. A first operating mode (OM) is implemented when |Vin|<a predetermined voltage level (PVL), where the control signal activates the main comparator. A second OM is implemented when |Vin|?PVL where the main differential pair is protected by switch from developing transient input offset voltage (VIO) offsets. Logic circuitry has logic inputs receiving outaux and outmain, and a logic output providing a decision result for the dual-comparator circuit using outmain when in the first OM and outaux when in the second OM.

Abstract: A bandgap reference (BGR) startup verification circuit includes a current minor for receiving an output current from a bandgap reference (BGR) circuit and generating output currents therefrom. A first verification sub-circuit is coupled to receive a first output current to generate a detection voltage (Vdet) and includes a voltage comparator receiving Vdet and a voltage output of the BGR circuit (VBG) to provide a first verification output. A second verification sub-circuit including a voltage comparator is coupled to receive a second output current and a second reference current and provide a second verification output. A third verification sub-circuit includes a current comparator coupled to receive a third output current and a third reference current and provide a third verification output. A digital state machine has inputs receiving the first, second and third verification output, and circuitry for processing these outputs to determine whether the BGR circuit has properly started.