Abstract: A method for adjusting timing of a secondary system with respect to a reference system is disclosed. The secondary and reference systems include a secondary synchronization signal and a reference synchronization signal, which are used to detect a phase difference between the secondary synchronization signal and the reference synchronization signal. A filtered phase error is generated from the detected phase difference. In addition, a frequency difference is detected between the secondary synchronization signal and the reference synchronization signal, and an instantaneous frequency difference and a filtered frequency error are generated from the detected frequency difference. The filtered phase error and the filtered frequency error are accumulated, and the timing of the secondary system is controlled in accordance with the accumulated filtered phase error, the accumulated filtered frequency error, and the instantaneous frequency difference.

Abstract: The frequency of use of video and other data is increasing. Additionally, video components are typically connected together. The video components may synchronize via a first in first out (“FIFO”) queue. Data may be written into the FIFO queue by a component with a first clock rate, and then the data may be read out of the FIFO queue by a component with a second clock rate. Because of the different clock rates, it is possible that there could be an underflow or overflow of data in the FIFO queue. Typically, when the timing between the components is far apart, the read and write pointers that point into the FIFO queue are realigned by using a reset control signal, which sets both pointers back to address zero of the FIFO queue. The present system provides an improved technique for synchronizing the read and write pointers. In particular, the present system provides a technique for aligning the read and write pointers of a FIFO queue at any time and at any random address.

Abstract: System and method for processing HDTV format video signals have been disclosed. A disclosed embodiment comprises a HDTV timing generator having as inputs a vertical sync and a horizontal sync. The HDTV timing generator outputs a digital HD level signal. The disclosed embodiment further comprises a DAC interface. The DAC interface can include an encoder channel, or more than one encoder channel. The encoder channel can receive a digital HD level signal, a SCART level signal, an NTSC level signal, a PAL level signal, and a SECAM level signal. The encoder channel can further receive a HDTV format data input, a SCART format data input, an NTSC format data input, a PAL format data input, and a SECAM format data input. The output of the DAC interface can be coupled to a DAC which in turn generates an output suitable for display on a monitor.