Abstract: Techniques for implementing dynamic simultaneous multi-threading (SMT) scheduling on a hybrid processor platforms are described. In certain examples, a hardware processor includes a first plurality of physical processor cores of a first type to implement a plurality of logical processor cores of the first type; a second plurality of physical processor cores of a second type, wherein each core of the second type is to implement a plurality of logical processor cores of the second type; and circuitry to: determine if a set of threads of a foreground application is to use more than a lower threshold (e.g., a threshold number (e.g., one) of logical processor cores) and less than or equal to an upper threshold (e.g.