Patents by Inventor Asit Mallick
Asit Mallick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230350687Abstract: Embodiments of instructions are detailed herein including one or more of 1) a branch fence instruction, prefix, or variants (BFENCE); 2) a predictor fence instruction, prefix, or variants (PFENCE); 3) an exception fence instruction, prefix, or variants (EFENCE); 4) an address computation fence instruction, prefix, or variants (AFENCE); 5) a register fence instruction, prefix, or variants (RFENCE); and, additionally, modes that apply the above semantics to some or all ordinary instructions.Type: ApplicationFiled: May 4, 2023Publication date: November 2, 2023Inventors: ROBERT S. CHAPPELL, JASON W. BRANDT, ALAN COX, ASIT MALLICK, JOSEPH NUZMAN, ARJAN VAN DE VEN
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Patent number: 11675594Abstract: Embodiments of instructions are detailed herein including one or more of 1) a branch fence instruction, prefix, or variants (BFENCE); 2) a predictor fence instruction, prefix, or variants (PFENCE); 3) an exception fence instruction, prefix, or variants (EFENCE); 4) an address computation fence instruction, prefix, or variants (AFENCE); 5) a register fence instruction, prefix, or variants (RFENCE); and, additionally, modes that apply the above semantics to some or all ordinary instructions.Type: GrantFiled: December 28, 2018Date of Patent: June 13, 2023Assignee: Intel CorporationInventors: Robert S. Chappell, Jason W. Brandt, Alan Cox, Asit Mallick, Joseph Nuzman, Arjan Van De Ven
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Patent number: 11630687Abstract: Embodiments of an invention related to compacted context state management are disclosed. In one embodiment, a processor includes instruction hardware and state management logic. The instruction hardware is to receive a first save instruction and a second save instruction. The state management logic is to, in response to the first save instruction, save context state in an un-compacted format in a first save area. The state management logic is also to, in response to the second save instruction, save a compaction mask and context state in a compacted format in a second save area and set a compacted-save indicator in the second save area. The state management logic is also to, in response to a single restore instruction, determine, based on the compacted-save indicator, whether to restore context from the un-compacted format in the first save area or from the compacted format in the second save area.Type: GrantFiled: February 20, 2018Date of Patent: April 18, 2023Assignee: Tahoe Research, Ltd.Inventors: Atul Khare, Leena Puthiyedath, Asit Mallick, Jim Coke, Michael Mishaeli, Gilbert Neiger, Vivekananthan Sanjeepan, Jason Brandt
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Publication number: 20230099517Abstract: Processors, methods, and systems for user-level interprocessor interrupts are described. In an embodiment, a processing system includes a memory and a processing core. The memory is to store an interrupt control data structure associated with a first application being executed by the processing system. The processing core includes an instruction decoder to decode a first instruction, invoked by a second application, to send an interprocessor interrupt to the first application; and, in response to the decoded instruction, is to determine that an identifier of the interprocessor interrupt matches a notification interrupt vector associated with the first application; set, in the interrupt control data structure, a pending interrupt flag corresponding to an identifier of the interprocessor interrupt; and invoke an interrupt handler for the interprocessor interrupt identified by the interrupt control data structure.Type: ApplicationFiled: December 23, 2021Publication date: March 30, 2023Applicant: Intel CorporationInventors: Gilbert Neiger, Asit Mallick, Rajesh Sankaran, Hisham Shafi, Vedvyas Shanbhogue, Vivekananthan Sanjeepan, Jason Brandt
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Publication number: 20220207147Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and execution circuitry coupled to the decode circuitry. The decode circuitry is to decode a register hardening instruction to mitigate vulnerability to a speculative execution attack. The execution circuitry is to be hardened in response to the register hardening instruction.Type: ApplicationFiled: December 26, 2020Publication date: June 30, 2022Applicant: Intel CorporationInventors: Carlos Rozas, Fangfei Liu, Xiang Zou, Francis McKeen, Jason W. Brandt, Joseph Nuzman, Alaa Alameldeen, Abhishek Basak, Scott Constable, Thomas Unterluggauer, Asit Mallick, Matthew Fernandez
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Publication number: 20220207148Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and branch circuitry coupled to the decode circuitry. The decode circuitry is to decode a branch hardening instruction to mitigate vulnerability to a speculative execution attack. The branch circuitry is to be hardened in response to the branch hardening instruction.Type: ApplicationFiled: December 26, 2020Publication date: June 30, 2022Applicant: Intel CorporationInventors: Carlos Rozas, Fangfei Liu, Xiang Zou, Francis McKeen, Jason W. Brandt, Joseph Nuzman, Alaa Alameldeen, Abhishek Basak, Scott Constable, Thomas Unterluggauer, Asit Mallick, Matthew Fernandez
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Publication number: 20220206818Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and execution circuitry coupled to the decode circuitry. The decode circuitry is to decode a single instruction to mitigate vulnerability to a speculative execution attack. The execution circuitry is to be hardened in response to the single instruction.Type: ApplicationFiled: December 26, 2020Publication date: June 30, 2022Applicant: Intel CorporationInventors: Alaa Alameldeen, Carlos Rozas, Fangfei Liu, Xiang Zou, Francis McKeen, Jason W. Brandt, Joseph Nuzman, Abhishek Basak, Scott Constable, Thomas Unterluggauer, Asit Mallick, Matthew Fernandez
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Publication number: 20220207146Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes decode circuitry and load circuitry coupled to the decode circuitry. The decode circuitry is to decode a load hardening instruction to mitigate vulnerability to a speculative execution attack. The load circuitry is to be hardened in response to the load hardening instruction.Type: ApplicationFiled: December 26, 2020Publication date: June 30, 2022Applicant: Intel CorporationInventors: Carlos Rozas, Fangfei Liu, Xiang Zou, Francis McKeen, Jason W. Brandt, Joseph Nuzman, Alaa Alameldeen, Abhishek Basak, Scott Constable, Thomas Unterluggauer, Asit Mallick, Matthew Fernandez
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Publication number: 20220207149Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes speculation vulnerability detection hardware and execution hardware. The speculation vulnerability detection hardware is to detect vulnerability to a speculative execution attack and, in connection with a detection of vulnerability to a speculative execution attack, to provide an indication that data from a first operation is tainted. The execution hardware is to perform a second operation using the data if the second operation is to be performed non-speculatively and to prevent performance of the second operation if the second operation is to be performed speculatively and the data is tainted.Type: ApplicationFiled: December 26, 2020Publication date: June 30, 2022Applicant: Intel CorporationInventors: Jason W. Brandt, Joseph Nuzman, Asit Mallick, Carlos Rozas
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Publication number: 20220207154Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes a hybrid key generator and memory protection hardware. The hybrid key generator is to generate a hybrid key based on a public key and multiple process identifiers. Each of the process identifiers corresponds to one or more memory spaces in a memory. The memory protection hardware is to use the first hybrid key to protect to the memory spaces.Type: ApplicationFiled: December 26, 2020Publication date: June 30, 2022Applicant: Intel CorporationInventors: Richard Winterton, Mohammad Reza Haghighat, Asit Mallick, Alaa Alameldeen, Abhishek Basak, Jason W. Brandt, Michael Chynoweth, Carlos Rozas, Scott Constable, Martin Dixon, Matthew Fernandez, Fangfei Liu, Francis McKeen, Joseph Nuzman, Gilles Pokam, Thomas Unterluggauer, Xiang Zou
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Publication number: 20220206819Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes speculation vulnerability mitigation hardware and speculation vulnerability detection hardware. The speculation vulnerability mitigation hardware is to implement one or more of a plurality of speculation vulnerability mitigation mechanisms. The speculation vulnerability detection hardware to detect vulnerability to a speculative execution attack and to provide to software an indication of speculative execution attack vulnerability.Type: ApplicationFiled: December 26, 2020Publication date: June 30, 2022Applicant: Intel CorporationInventors: Gilles Pokam, Asit Mallick, Martin Dixon, Michael Chynoweth
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Publication number: 20220207138Abstract: Embodiments for dynamically mitigating speculation vulnerabilities are disclosed. In an embodiment, an apparatus includes a decode circuitry and store circuitry coupled to the decode circuitry. The decode circuitry is to decode a store hardening instruction to mitigate vulnerability to a speculative execution attack. The store circuitry is to be hardened in response to the store hardening instruction.Type: ApplicationFiled: December 26, 2020Publication date: June 30, 2022Applicant: Intel CorporationInventors: Carlos Rozas, Fangfei Liu, Xiang Zou, Francis McKeen, Jason W. Brandt, Joseph Nuzman, Alaa Alameldeen, Abhishek Basak, Scott Constable, Thomas Unterluggauer, Asit Mallick, Matthew Fernandez
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Publication number: 20190324756Abstract: Embodiments of instructions are detailed herein including one or more of 1) a branch fence instruction, prefix, or variants (BFENCE); 2) a predictor fence instruction, prefix, or variants (PFENCE); 3) an exception fence instruction, prefix, or variants (EFENCE); 4) an address computation fence instruction, prefix, or variants (AFENCE); 5) a register fence instruction, prefix, or variants (RFENCE); and, additionally, modes that apply the above semantics to some or all ordinary instructions.Type: ApplicationFiled: December 28, 2018Publication date: October 24, 2019Inventors: ROBERT S. CHAPPELL, JASON W. BRANDT, ALAN COX, ASIT MALLICK, JOSEPH NUZMAN, ARJAN VAN DE VEN
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Patent number: 10120805Abstract: A processing device includes a conflict resolution logic circuit to initiate a tracking phase to track translation look aside buffer (TLB) mappings to an enclave memory cache (EPC) page of a secure enclave. The conflict resolution logic circuit is further to execute a tracking instruction as part of the tracking phase, wherein the tracking instruction takes any page in the secure enclave as an argument parameter to the tracking instruction.Type: GrantFiled: January 18, 2017Date of Patent: November 6, 2018Assignee: Intel CorporationInventors: Rebekah M. Leslie-Hurd, Francis X. McKeen, Carlos V. Rozas, Gilbert Neiger, Asit Mallick, Ittai Anati, Ilya Alexandrovich, Vedvyas Shanbhogue, Somnath Chakrabarti
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Publication number: 20180276027Abstract: Embodiments of an invention related to compacted context state management are disclosed. In one embodiment, a processor includes instruction hardware and state management logic. The instruction hardware is to receive a first save instruction and a second save instruction. The state management logic is to, in response to the first save instruction, save context state in an un-compacted format in a first save area. The state management logic is also to, in response to the second save instruction, save a compaction mask and context state in a compacted format in a second save area and set a compacted-save indicator in the second save area. The state management logic is also to, in response to a single restore instruction, determine, based on the compacted-save indicator, whether to restore context from the un-compacted format in the first save area or from the compacted format in the second save area.Type: ApplicationFiled: February 20, 2018Publication date: September 27, 2018Inventors: Atul KHARE, Leena PUTHIYEDATH, Asit MALLICK, Jim COKE, Michael MISHAELI, Gilbert NEIGER, Vivekananthan SANJEEPAN, Jason BRANDT
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Publication number: 20180203801Abstract: A processing device includes a conflict resolution logic circuit to initiate a tracking phase to track translation look aside buffer (TLB) mappings to an enclave memory cache (EPC) page of a secure enclave. The conflict resolution logic circuit is further to execute a tracking instruction as part of the tracking phase, wherein the tracking instruction takes any page in the secure enclave as an argument parameter to the tracking instruction.Type: ApplicationFiled: January 18, 2017Publication date: July 19, 2018Inventors: Rebekah M. Leslie-Hurd, Francis X. McKeen, Carlos V. Rozas, Gilbert Neiger, Asit Mallick, Ittai Anati, Ilya Alexandrovich, Vedvyas Shanbhogue, Somnath Chakrabarti
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Patent number: 9977743Abstract: A processing device includes a first counter having a first count value of a number of child pages among a plurality of child pages present in an enclave memory of a first virtual machine (VM). The plurality of child pages are associated with a parent page in the enclave memory. The processing device includes a second counter having a second count value of a number of child pages among the plurality of child pages not present in the enclave memory and being shared by a second VM, wherein the second VM is different from the first VM. A non-zero value of at least one of the first counter or the second counter prevents eviction of the parent page from the enclave memory.Type: GrantFiled: August 31, 2016Date of Patent: May 22, 2018Assignee: Intel CorporationInventors: Rebekah M. Leslie-Hurd, Francis X. McKeen, Carlos V. Rozas, Somnath Chakrabarti, Asit Mallick
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Publication number: 20180060237Abstract: A processing device includes a first counter having a first count value of a number of child pages among a plurality of child pages present in an enclave memory of a first virtual machine (VM). The plurality of child pages are associated with a parent page in the enclave memory. The processing device includes a second counter having a second count value of a number of child pages among the plurality of child pages not present in the enclave memory and being shared by a second VM, wherein the second VM is different from the first VM. A non-zero value of at least one of the first counter or the second counter prevents eviction of the parent page from the enclave memory.Type: ApplicationFiled: August 31, 2016Publication date: March 1, 2018Inventors: Rebekah M. Leslie-Hurd, Francis X. McKeen, Carlos V. Rozas, Somnath Chakrabarti, Asit Mallick
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Patent number: 9898330Abstract: Embodiments of an invention related to compacted context state management are disclosed. In one embodiment, a processor includes instruction hardware and state management logic. The instruction hardware is to receive a first save instruction and a second save instruction. The state management logic is to, in response to the first save instruction, save context state in an un-compacted format in a first save area. The state management logic is also to, in response to the second save instruction, save a compaction mask and context state in a compacted format in a second save area and set a compacted-save indicator in the second save area. The state management logic is also to, in response to a single restore instruction, determine, based on the compacted-save indicator, whether to restore context from the un-compacted format in the first save area or from the compacted format in the second save area.Type: GrantFiled: November 11, 2013Date of Patent: February 20, 2018Assignee: Intel CorporationInventors: Atul Khare, Leena Puthiyedath, Asit Mallick, Jim Coke, Michael Mishaeli, Gilbert Neiger, Vivekananthan Sanjeepan, Jason Brandt
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Patent number: 9600283Abstract: Methods and apparatuses for reducing power consumption of processor switch operations are disclosed. One or more embodiments may comprise specifying a subset of registers or state storage elements to be involved in a register or state storage operation, performing the register or state storage operation, and performing a switch operation. The embodiments may minimize the number of registers or state storage elements involved with the standby operation by specifying only the subset of registers or state storage elements, which may involve considerably fewer than the total number of registers or state storage or elements of the processor. The switch operation may be switch from one mode to another, such as a transition to or from a sleep mode, a context switch, or the execution of various types of instructions.Type: GrantFiled: September 15, 2015Date of Patent: March 21, 2017Assignee: Intel CorporationInventors: Ethan Schuchman, Hong Wang, Chris Weaver, Belliappa M. Kuttanna, Asit Mallick, Vivek K. De, Per Hammarlund