Abstract: A phase detector for high speed logic circuits including an edge detector circuit responsive to two signals which may contain frequency and phase errors which result in the edges of the signal pulses of the two signals occurring at different times. The edges of the two signal pulses are detected by a phase detector circuit and an output signal provided to a correction circuit that provides a correction signal for the time period between the pulse edges of the signal pulses. The correction circuit output signal is fed back to a local oscillator to minimize the frequency and phase errors. A synchronizing circuit is connected to the output of the correction circuit to synchronously reset the phase detector circuit at the end of the correction signal period.