Abstract: An external nonvolatile memory device that includes a rewritable nonvolatile memory and a CMOS interface is disclosed. The interface includes a clock signal which is input to the external nonvolatile memory device. This clock signal is multiplied by an integer to create a memory serdes clock which is used to clock outgoing data. The memory serdes clock is also used to create a clock that is used to clock the incoming data from the main processing device. The external nonvolatile memory device also includes an encryption/decryption block that encrypts data read from the nonvolatile memory before it is transmitted over the interface, and decrypts data received from the interface before storing it in the nonvolatile memory. The encryption/decryption block may utilize a stream cipher.

Abstract: An interface between two devices is disclosed. To consume power, the signals used in the interface utilize CMOS signalling. Further, to achieve high speed, a reduced frequency clock is transmitted from one device to the second device. The second device has a clock multiplier to recreate the original clock. Both devices utilize a clock phase alignment block which aligns the phase of the clock with the incoming data. The clock phase alignment block utilizes a digital PLL to consume power. Further, since the digital PLL retains its state, the reduced frequency clock may be disabled when data is not being transmitted. This interface may be used to transmit serial data at rates up to and exceeding 2.5 Gbits/sec.

Abstract: An external nonvolatile memory device that includes a rewritable nonvolatile memory and a CMOS interface is disclosed. The interface includes a clock signal which is input to the external nonvolatile memory device. This clock signal is multiplied by an integer to create a memory serdes clock which is used to clock outgoing data. The memory serdes clock is also used to create a clock that is used to clock the incoming data from the main processing device. The external nonvolatile memory device also includes an encryption/decryption block that encrypts data read from the nonvolatile memory before it is transmitted over the interface, and decrypts data received from the interface before storing it in the nonvolatile memory. The encryption/decryption block may utilize a stream cipher.

Abstract: An interface between two devices is disclosed. To consume power, the signals used in the interface utilize CMOS signalling. Further, to achieve high speed, a reduced frequency clock is transmitted from one device to the second device. The second device has a clock multiplier to recreate the original clock. Both devices utilize a clock phase alignment block which aligns the phase of the clock with the incoming data. The clock phase alignment block utilizes a digital PLL to consume power. Further, since the digital PLL retains its state, the reduced frequency clock may be disabled when data is not being transmitted. This interface may be used to transmit serial data at rates up to and exceeding 2.5 Gbits/sec.

Abstract: A wireless communication device is disclosed wherein the voltage swing of a local oscillator (LO) signal is controlled to prevent overstressing semiconductor devices in a mixer to which the LO signal is supplied. A quadrature divider supplies the LO signal to the mixer. Digital calibration methodology controls the current that the quadrature divider draws from a power supply to set the voltage swing of the LO signal that the quadrature divider generates.

Abstract: In one embodiment, a local oscillator and mixer architecture may include a frequency divider having I and Q channel master storage elements formed of devices of a first size, and I and Q channel slave storage elements formed of devices of a second size, where the second size is smaller than the first size. In such manner, power consumption may be reduced while reducing phase noise in signals provided from the frequency divider to the corresponding mixer.

Abstract: A wireless communication device is disclosed wherein the voltage swing of a local oscillator (LO) signal is controlled to prevent overstressing semiconductor devices in a mixer to which the LO signal is supplied. A quadrature divider supplies the LO signal to the mixer. Digital calibration methodology controls the current that the quadrature divider draws from a power supply to set the voltage swing of the LO signal that the quadrature divider generates.

Abstract: A wireless communication device is disclosed wherein the voltage swing of a local oscillator (LO) signal is controlled to prevent overstressing semiconductor devices in a mixer to which the LO signal is supplied. A quadrature divider supplies the LO signal to the mixer. Digital calibration methodology controls the current that the quadrature divider draws from a power supply to set the voltage swing of the LO signal that the quadrature divider generates.

Abstract: In one embodiment, the present invention includes a frequency divider that has an I channel to provide an I channel phase; and a Q channel to provide a Q channel phase, in which the I and the Q channels are mirrored with respect to an axis therebetween. The axis may also be substantially coincident with a center axis of a device incorporating the frequency divider, such as a transceiver.

Abstract: In one embodiment, a local oscillator and mixer architecture may include a frequency divider having I and Q channel master storage elements formed of devices of a first size, and I and Q channel slave storage elements formed of devices of a second size, where the second size is smaller than the first size. In such manner, power consumption may be reduced while reducing phase noise in signals provided from the frequency divider to the corresponding mixer.