Abstract: Nested phase-locked loops (PLLs) utilize resonators of different quality factors, oscillation frequencies, and tunability. A reference clock signal for a first PLL is based on a free running bulk acoustic wave (BAW) resonator. The first PLL utilizes an LC oscillator as a voltage controlled oscillator. A crystal oscillator supplies a reference clock signal to a second PLL. Feedback dividers of the first and second PLLs are coupled to the LC oscillator. A delta sigma modulator coupled to the loop filter of the second PLL controls the feedback divider of the first PLL. The first PLL utilizes a high update rate to ensure that the jitter power spectral density is spread over a wide frequency range. The nested PLL architecture allows the overall phase noise plot to follow that of the crystal resonator at low frequencies, the BAW resonator at mid-frequencies, and the LC resonator at high frequencies.

Abstract: Nested phase-locked loops (PLLs) utilize resonators of different quality factors, oscillation frequencies, and tunability. A reference clock signal for a first PLL is based on a free running bulk acoustic wave (BAW) resonator. The first PLL utilizes an LC oscillator as a voltage controlled oscillator. A crystal oscillator supplies a reference clock signal to a second PLL. Feedback dividers of the first and second PLLs are coupled to the LC oscillator. A delta sigma modulator coupled to the loop filter of the second PLL controls the feedback divider of the first PLL. The first PLL utilizes a high update rate to ensure that the jitter power spectral density is spread over a wide frequency range. The nested PLL architecture allows the overall phase noise plot to follow that of the crystal resonator at low frequencies, the BAW resonator at mid-frequencies, and the LC resonator at high frequencies.

Abstract: A system and method for accurately determining a distance between two network devices using a Channel Sounding application is disclosed. The network devices each guarantee a fixed phase relationship between the transmit circuit and the receive circuit. In one embodiment, this is achieved by incorporating the divider within the phase locked loop. The divider may have a reset, such that it can be initialized to a predetermined state. Further, by utilizing a divider disposed within the phase locked loop with a reset, the quadrature signal generator is guaranteed to output clocks for the transmit circuit and the receive circuit that have a constant phase relationship.

Abstract: A phase and frequency detector receives a reference clock signal with a period error and receives a feedback clock signal from a feedback divider. The feedback divider circuit divides a clock signal from a voltage controlled oscillator. The feedback divider divides by different divide values during odd and even cycles of the reference clock signal to cause the feedback clock signal to have a period error that substantially matches the period error of the reference clock signal. The divider values supplied to the feedback divider are determined, at least in part, by the period error of the reference clock signal.

Abstract: A phase and frequency detector receives a reference clock signal with a period error and receives a feedback clock signal from a feedback divider. The feedback divider circuit divides a clock signal from a voltage controlled oscillator. The feedback divider divides by different divide values during odd and even cycles of the reference clock signal to cause the feedback clock signal to have a period error that substantially matches the period error of the reference clock signal. The divider values supplied to the feedback divider are determined, at least in part, by the period error of the reference clock signal.

Abstract: A fractional-N phase-locked loop (PLL) has a time-to-voltage converter with second order non linearity. The time-to voltage-converter provides an analog error signal indicating a phase difference between the reference clock signal with a period error and a feedback signal supplied by a fractional-N feedback divider. The spur results in quantization noise associated with the fractional-N feedback divider being frequency translated. To address the frequency translated noise, a spur cancellation circuit receives a residue signal indicative of the quantization noise and a spur signal indicative of the spur. The non-linearity of the time-to-voltage converter is mimicked digitally through terms of a polynomial generated to cancel the noise. The generated polynomial is coupled to a delta sigma modulator that controls a digital to analog converter that adds/subtracts a voltage value to/from the error signal to thereby cancel the quantization noise including the frequency translated quantization noise.

Abstract: A sine to square wave converter circuit receives a sine wave signal and supplies a first square wave signal having a first frequency. A 2× clock multiplier circuit multiplies the first square wave signal and supplies a second square wave signal with a second frequency that is twice the first frequency. A first storage element that is clocked by the second square wave signal stores a delayed version of the first square wave signal and supplies an even-odd signal. A second storage element that is clocked by the second square wave signal receives the even-odd signal and supplies an odd-even signal. A duty cycle correction circuit adjusts the threshold of the sine to square wave converter based on a difference in duty pulse widths between the even-odd signal and the odd-even signal.

Abstract: In one embodiment, an apparatus includes a voltage controlled oscillator (VCO) to output an oscillating signal. The VCO may have a tank formed of at least one capacitor coupled in parallel with at least one inductor, and a plurality of transconductors to provide energy to the tank. At least one of the plurality of transconductors can be controllably switched to be coupled to the tank or to be decoupled from the tank.

Abstract: In an embodiment, an apparatus includes: a transmit circuit to upconvert a baseband signal to a first differential radio frequency (RF) signal, the transmit circuit to convert the first differential RF signal to a first single-ended RF signal; a duty cycle correction circuit coupled to the transmit circuit to receive the first single-ended RF signal and compensate for a duty cycle variation in the first single-ended RF signal to output a duty cycle-corrected RF signal; a conversion circuit to convert the duty cycle-corrected RF signal to a second differential RF signal; and an interface circuit to transfer the second differential RF signal from a first ground domain to a second ground domain.

Abstract: In one embodiment, an apparatus includes a voltage controlled oscillator (VCO) to output an oscillating signal. The VCO may have a tank formed of at least one capacitor coupled in parallel with at least one inductor, and a plurality of transconductors to provide energy to the tank. At least one of the plurality of transconductors can be controllably switched to be coupled to the tank or to be decoupled from the tank.

Abstract: A technique that reduces or eliminates trading-off power amplifier efficiency and costly external filtering in amplitude and phase modulated sinusoidal signal generation uses multi-phase outphasing and a multi-phase switching mode power amplifier to generate the amplitude and phase modulated sinusoidal signals. The technique combines multiple clock phases with sinusoidally weighted circuits of the switching mode power amplifier to improve amplitude and phase modulated sinusoidal signal generation.

Abstract: A technique that reduces or eliminates trading-off power amplifier efficiency and costly external filtering in amplitude and phase modulated sinusoidal signal generation uses multi-phase outphasing and a multi-phase switching mode power amplifier to generate the amplitude and phase modulated sinusoidal signals. The technique combines multiple clock phases with sinusoidally weighted circuits of the switching mode power amplifier to improve amplitude and phase modulated sinusoidal signal generation.

Abstract: A technique that reduces or eliminates trading-off power amplifier efficiency and costly external filtering in amplitude and phase modulated sinusoidal signal generation uses multi-phase outphasing and a multi-phase switching mode power amplifier to generate the amplitude and phase modulated sinusoidal signals. The technique combines multiple clock phases with sinusoidally weighted circuits of the switching mode power amplifier to improve amplitude and phase modulated sinusoidal signal generation.

Abstract: An apparatus includes a signal generator. The signal generator includes a voltage controlled oscillator (VCO) coupled to provide an output signal having a frequency. The signal generator further includes an asymmetric divider coupled to receive the output signal of the VCO and to provide an output signal. The output signal of the asymmetric divider has a frequency that is half the frequency of the output signal of the VCO. The asymmetric divider presents a balanced load to the VCO.

Abstract: Apparatus and methods are disclosed that utilize magnetically differential loop filter capacitor elements that are physically positioned adjacent voltage-controlled oscillator (VCO) inductor/s in the device layout of a phase locked loop (PLL) circuit. Such a PLL circuit may be employed, for example, to produce a PLL output signal for RF receivers, RF transmitters, RF transceivers and any other type of circuit configured to utilize a PLL output signal having a phase that is based on the phase of an input signal.

Abstract: An apparatus includes a signal generator. The signal generator includes a voltage controlled oscillator (VCO) coupled to provide an output signal having a frequency. The signal generator further includes an asymmetric divider coupled to receive the output signal of the VCO and to provide an output signal. The output signal of the asymmetric divider has a frequency that is half the frequency of the output signal of the VCO. The asymmetric divider presents a balanced load to the VCO.

Abstract: An apparatus includes a signal generator. The signal generator includes a voltage controlled oscillator (VCO) coupled to provide an output signal having a frequency. The signal generator further includes an asymmetric divider coupled to receive the output signal of the VCO and to provide an output signal. The output signal of the asymmetric divider has a frequency that is lower than the frequency of the output signal of the VCO. The asymmetric divider presents a balanced load to the VCO.

Abstract: A receiver comprises a passive gain stage having an input to receive an in-going radio frequency (RF) signal and a gain control signal to produce an adjusted in-going RF signal, a sliced LNA stage comprising a plurality of LNAs coupled to receive the in-going RF signal. Each LNA includes an adjustable source degeneration circuit for receiving a plurality of gain selection and control signals and an output port to produce an amplified in-going RF signal. A mixer is coupled to receive at least one of the amplified in-going RF signals produced by the sliced LNA stage and is configured to produce a converted signal at another frequency. A PGA is coupled to receive the down-converted signal and produces an amplified in-going signal.

Abstract: A transceiver includes a transmit/receive terminal, a receiver input terminal, a plurality of impedance transformation networks coupled in series, a plurality of power amplifiers, and a controller. Each impedance transformation network has first and second ports. The impedance transformation networks include at least one selectable impedance transformation network having a resonant mode and a termination mode. The power amplifiers have outputs respectively coupled to the second ports of corresponding ones of the impedance transformation networks. In a receive mode, the controller selects the resonant mode for each selectable impedance transformation network and disables all power amplifiers. In a transmit mode, the controller enables a selected power amplifier and selects the resonant mode of any upstream selectable impedance transformation network, and selects the termination mode of a downstream selectable impedance transformation network.

Abstract: A receiver comprises a passive gain stage having an input to receive an in-going radio frequency (RF) signal and a gain control signal to produce an adjusted in-going RF signal, a sliced LNA stage comprising a plurality of LNAs coupled to receive the in-going RF signal. Each LNA includes an adjustable source degeneration circuit for receiving a plurality of gain selection and control signals and an output port to produce an amplified in-going RF signal. A mixer is coupled to receive at least one of the amplified in-going RF signals produced by the sliced LNA stage and is configured to produce a converted signal at another frequency. A PGA is coupled to receive the down-converted signal and produces an amplified in-going signal.