Patents by Inventor Asli Sirman

Asli Sirman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190355624
    Abstract: Methods produce integrated circuit structures that include (among other components) fins extending from a first layer, source/drain structures on the fins, source/drain contacts on the source/drain structures, an insulator on the source/drain contacts defining trenches between the source/drain contacts, gate conductors in a lower portion of the trenches adjacent the fins, a first liner material lining a middle portion and an upper portion of the trenches, a fill material in the middle portion of the trenches, and a second material in the upper portion of the trenches. The first liner material is on the gate conductors in the trenches.
    Type: Application
    Filed: August 1, 2019
    Publication date: November 21, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Asli Sirman, Jiehui Shu, Chih-Chiang Chang, Huy Cao, Haigou Huang, Jinping Liu
  • Publication number: 20190326112
    Abstract: A method of cleaning a low-k spacer cavity by a low energy RF plasma at a specific substrate temperature for a defect free epitaxial growth of Si, SiGe, Ge, III-V and III-N and the resulting device are provided. Embodiments include providing a substrate with a low-k spacer cavity; cleaning the low-k spacer cavity with a low energy RF plasma at a substrate temperature between room temperature to 600° C.; and forming an epitaxy film or a RSD in the low-k spacer cavity subsequent to the low energy RF plasma cleaning.
    Type: Application
    Filed: April 19, 2018
    Publication date: October 24, 2019
    Inventors: Shahab SIDDIQUI, Hamed PARVANEH, Mira PARK, Annie LEVESQUE, Yinxiao YANG, Hongyi MI, Asli SIRMAN
  • Publication number: 20190304843
    Abstract: Methods produce integrated circuit structures that include (among other components) fins extending from a first layer, source/drain structures on the fins, source/drain contacts on the source/drain structures, an insulator on the source/drain contacts defining trenches between the source/drain contacts, gate conductors in a lower portion of the trenches adjacent the fins, a first liner material lining a middle portion and an upper portion of the trenches, a fill material in the middle portion of the trenches, and a second material in the upper portion of the trenches. The first liner material is on the gate conductors in the trenches.
    Type: Application
    Filed: March 27, 2018
    Publication date: October 3, 2019
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Asli Sirman, Jiehui Shu, Chih-Chiang Chang, Huy Cao, Haigou Huang, Jinping Liu
  • Patent number: 10431500
    Abstract: Methods produce integrated circuit structures that include (among other components) fins extending from a first layer, source/drain structures on the fins, source/drain contacts on the source/drain structures, an insulator on the source/drain contacts defining trenches between the source/drain contacts, gate conductors in a lower portion of the trenches adjacent the fins, a first liner material lining a middle portion and an upper portion of the trenches, a fill material in the middle portion of the trenches, and a second material in the upper portion of the trenches. The first liner material is on the gate conductors in the trenches.
    Type: Grant
    Filed: March 27, 2018
    Date of Patent: October 1, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Asli Sirman, Jiehui Shu, Chih-Chiang Chang, Huy Cao, Haigou Huang, Jinping Liu
  • Publication number: 20190211467
    Abstract: A method for high rate assembly of nanoelements into two-dimensional void patterns on a non-conductive substrate surface utilizes an applied electric field to stabilize against forces resulting from pulling the substrate through the surface of a nanoelement suspension. The electric field contours emanating from a conductive layer in the substrate, covered by an insulating layer, are modified by a patterned photoresist layer, resulting in an increased driving force for nanoelements to migrate from a liquid suspension to voids on a patterned substrate having a non-conductive surface. The method can be used for the production of microscale and nanoscale circuits, sensors, and other electronic devices.
    Type: Application
    Filed: March 19, 2019
    Publication date: July 11, 2019
    Inventors: Asli Sirman, Ahmed Busnaina, Cihan Yilmaz, Jun Huang, Sivasubramanian Somu
  • Patent number: 10233559
    Abstract: A method for high rate assembly of nanoelements into two-dimensional void patterns on a non-conductive substrate surface utilizes an applied electric field to stabilize against forces resulting from pulling the substrate through the surface of a nanoelement suspension. The electric field contours emanating from a conductive layer in the substrate, covered by an insulating layer, are modified by a patterned photoresist layer, resulting in an increased driving force for nanoelements to migrate from a liquid suspension to voids on a patterned substrate having a non-conductive surface. The method can be used for the production of microscale and nanoscale circuits, sensors, and other electronic devices.
    Type: Grant
    Filed: November 14, 2016
    Date of Patent: March 19, 2019
    Assignee: Northeastern University
    Inventors: Asli Sirman, Ahmed Busnaina, Cihan Yilmaz, Jun Huang, Sivasubramanian Somu
  • Patent number: 10192791
    Abstract: A method of forming a robust low-k sidewall spacer by exposing an upper portion of the spacer to a thermal and plasma treatment prior to downstream processes and resulting device are provided. Embodiments include providing a pair of gates separated by a canyon trench over a substrate, an EPI layer in a bottom of the canyon trench, respectively, and a low-k spacer on each opposing sidewall of the pair; forming a masking layer in a bottom portion of the canyon trench, an upper portion of the low-k spacers exposed; and treating the upper portion of the low-k spacers with a thermal and plasma treatment.
    Type: Grant
    Filed: March 6, 2018
    Date of Patent: January 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Man Gu, Tao Han, Junsic Hong, Jiehui Shu, Asli Sirman, Charlotte Adams, Jinping Liu, Keith Tabakman
  • Publication number: 20170058422
    Abstract: A method for high rate assembly of nanoelements into two-dimensional void patterns on a non-conductive substrate surface utilizes an applied electric field to stabilize against forces resulting from pulling the substrate through the surface of a nanoelement suspension. The electric field contours emanating from a conductive layer in the substrate, covered by an insulating layer, are modified by a patterned photoresist layer, resulting in an increased driving force for nanoelements to migrate from a liquid suspension to voids on a patterned substrate having a non-conductive surface. The method can be used for the production of microscale and nanoscale circuits, sensors, and other electronic devices.
    Type: Application
    Filed: November 14, 2016
    Publication date: March 2, 2017
    Inventors: Asli Sirman, Ahmed Busnaina, Cihan Yilmaz, Jun Huang, Sivasubramanian Somu
  • Patent number: 9497855
    Abstract: A method for high rate assembly of nanoelements into two-dimensional void patterns on a non-conductive substrate surface utilizes an applied electric field to stabilize against forces resulting from pulling the substrate through the surface of a nanoelement suspension. The electric field contours emanating from a conductive layer in the substrate, covered by an insulating layer, are modified by a patterned photoresist layer, resulting in an increased driving force for nanoelements to migrate from a liquid suspension to voids on a patterned substrate having a non-conductive surface. The method can be used for the production of microscale and nanoscale circuits, sensors, and other electronic devices.
    Type: Grant
    Filed: August 28, 2015
    Date of Patent: November 15, 2016
    Assignee: Northeastern University
    Inventors: Asli Sirman, Ahmed Busnaina, Cihan Yilmaz, Jun Huang, Sivasubramanian Somu
  • Publication number: 20160021738
    Abstract: A method for high rate assembly of nanoelements into two-dimensional void patterns on a non-conductive substrate surface utilizes an applied electric field to stabilize against forces resulting from pulling the substrate through the surface of a nanoelement suspension. The electric field contours emanating from a conductive layer in the substrate, covered by an insulating layer, are modified by a patterned photoresist layer, resulting in an increased driving force for nanoelements to migrate from a liquid suspension to voids on a patterned substrate having a non-conductive surface. The method can be used for the production of microscale and nanoscale circuits, sensors, and other electronic devices.
    Type: Application
    Filed: August 28, 2015
    Publication date: January 21, 2016
    Inventors: Asli Sirman, Ahmed Busnaina, Cihan Yilmaz, Jun Huang, Sivasubramanian Somu
  • Patent number: 9145618
    Abstract: A method for high rate assembly of nanoelements into two-dimensional void patterns on a non-conductive substrate surface utilizes an applied electric field to stabilize against forces resulting from pulling the substrate through the surface of a nanoelement suspension. The electric field contours emanating from a conductive layer in the substrate, covered by an insulating layer, are modified by a patterned photoresist layer, resulting in an increased driving force for nanoelements to migrate from a liquid suspension to voids on a patterned substrate having a non-conductive surface. The method can be used for the production of microscale and nanoscale circuits, sensors, and other electronic devices.
    Type: Grant
    Filed: November 29, 2011
    Date of Patent: September 29, 2015
    Assignee: Northeastern University
    Inventors: Asli Sirman, Ahmed Busnaina, Cihan Yilmaz, Jun Huang, Sivasubramanian Somu
  • Publication number: 20130256013
    Abstract: A method for high rate assembly of nanoelements into two-dimensional void patterns on a non-conductive substrate surface utilizes an applied electric field to stabilize against forces resulting from pulling the substrate through the surface of a nanoelement suspension. The electric field contours emanating from a conductive layer in the substrate, covered by an insulating layer, are modified by a patterned photoresist layer, resulting in an increased driving force for nanoelements to migrate from a liquid suspension to voids on a patterned substrate having a non-conductive surface. The method can be used for the production of micro scale and nanoscale circuits, sensors, and other electronic devices.
    Type: Application
    Filed: November 29, 2011
    Publication date: October 3, 2013
    Applicant: NORTHEASTERN UNIVERSITY
    Inventors: Asli Sirman, Ahmed Busnaina, Cihan Yilmaz, Jun Huang, Sivasubramanian Somu