Patents by Inventor Asli Sirman
Asli Sirman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20230171988Abstract: An electronic device may have a display such as an organic light-emitting diode display. The organic light-emitting diode (OLED) display may have an array of organic light-emitting diode pixels that each have OLED layers interposed between a cathode and an anode. A first passivation layer, a first planarization layer, and a second passivation layer may be formed over the cathode. The first and second passivation layers may be formed from inorganic material. A second planarization layer may be formed over the second passivation layer between the second passivation layer and a polarizer. The second planarization layer may planarize the polarizer at the edges of the active area of the display where the polarizer would otherwise have a steep taper. Planarizing the polarizer in this way mitigates undesirable secondary reflections off of the polarizer. The first and second planarization layers may be formed from organic material.Type: ApplicationFiled: October 18, 2022Publication date: June 1, 2023Inventors: Prashant Mandlik, Bhadrinarayana Lalgudi Visweswaran, Ankit Mahajan, Chia-Hao Chang, Christopher E Glazowski, David L Wei, Hui Lu, Takahide Ishii, Themistoklis Afentakis, Han Liu, Cheng-Chih Hsieh, Asli Sirman, Shih Chang Chang, Ko-Wei Chen, Shang-Chih Lin, Tsung-Ting Tsai, Jae Won Choi, Abbas Jamshidi Roudbari, Ting-Kuo Chang, Jean-Pierre S Guillou
-
Patent number: 10964599Abstract: Methods produce integrated circuit structures that include (among other components) fins extending from a first layer, source/drain structures on the fins, source/drain contacts on the source/drain structures, an insulator on the source/drain contacts defining trenches between the source/drain contacts, gate conductors in a lower portion of the trenches adjacent the fins, a first liner material lining a middle portion and an upper portion of the trenches, a fill material in the middle portion of the trenches, and a second material in the upper portion of the trenches. The first liner material is on the gate conductors in the trenches.Type: GrantFiled: August 1, 2019Date of Patent: March 30, 2021Assignee: GLOBALFOUNDRIES U.S. Inc.Inventors: Asli Sirman, Jiehui Shu, Chih-Chiang Chang, Huy Cao, Haigou Huang, Jinping Liu
-
Publication number: 20200312775Abstract: A semiconductor device structure is provided that includes a dielectric layer and a barrier layer having at least two layers of two dimensional materials on the dielectric layer, wherein each layer is made of a different two dimensional material.Type: ApplicationFiled: March 28, 2019Publication date: October 1, 2020Inventors: RINUS TEK PO LEE, FUAD AL-AMOODY, ASLI SIRMAN, JOSEPH KYALO KASSIM, HUI ZANG, BHARAT V. KRISHNAN
-
Publication number: 20190355624Abstract: Methods produce integrated circuit structures that include (among other components) fins extending from a first layer, source/drain structures on the fins, source/drain contacts on the source/drain structures, an insulator on the source/drain contacts defining trenches between the source/drain contacts, gate conductors in a lower portion of the trenches adjacent the fins, a first liner material lining a middle portion and an upper portion of the trenches, a fill material in the middle portion of the trenches, and a second material in the upper portion of the trenches. The first liner material is on the gate conductors in the trenches.Type: ApplicationFiled: August 1, 2019Publication date: November 21, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Asli Sirman, Jiehui Shu, Chih-Chiang Chang, Huy Cao, Haigou Huang, Jinping Liu
-
Publication number: 20190326112Abstract: A method of cleaning a low-k spacer cavity by a low energy RF plasma at a specific substrate temperature for a defect free epitaxial growth of Si, SiGe, Ge, III-V and III-N and the resulting device are provided. Embodiments include providing a substrate with a low-k spacer cavity; cleaning the low-k spacer cavity with a low energy RF plasma at a substrate temperature between room temperature to 600° C.; and forming an epitaxy film or a RSD in the low-k spacer cavity subsequent to the low energy RF plasma cleaning.Type: ApplicationFiled: April 19, 2018Publication date: October 24, 2019Inventors: Shahab SIDDIQUI, Hamed PARVANEH, Mira PARK, Annie LEVESQUE, Yinxiao YANG, Hongyi MI, Asli SIRMAN
-
Publication number: 20190304843Abstract: Methods produce integrated circuit structures that include (among other components) fins extending from a first layer, source/drain structures on the fins, source/drain contacts on the source/drain structures, an insulator on the source/drain contacts defining trenches between the source/drain contacts, gate conductors in a lower portion of the trenches adjacent the fins, a first liner material lining a middle portion and an upper portion of the trenches, a fill material in the middle portion of the trenches, and a second material in the upper portion of the trenches. The first liner material is on the gate conductors in the trenches.Type: ApplicationFiled: March 27, 2018Publication date: October 3, 2019Applicant: GLOBALFOUNDRIES INC.Inventors: Asli Sirman, Jiehui Shu, Chih-Chiang Chang, Huy Cao, Haigou Huang, Jinping Liu
-
Patent number: 10431500Abstract: Methods produce integrated circuit structures that include (among other components) fins extending from a first layer, source/drain structures on the fins, source/drain contacts on the source/drain structures, an insulator on the source/drain contacts defining trenches between the source/drain contacts, gate conductors in a lower portion of the trenches adjacent the fins, a first liner material lining a middle portion and an upper portion of the trenches, a fill material in the middle portion of the trenches, and a second material in the upper portion of the trenches. The first liner material is on the gate conductors in the trenches.Type: GrantFiled: March 27, 2018Date of Patent: October 1, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Asli Sirman, Jiehui Shu, Chih-Chiang Chang, Huy Cao, Haigou Huang, Jinping Liu
-
Publication number: 20190211467Abstract: A method for high rate assembly of nanoelements into two-dimensional void patterns on a non-conductive substrate surface utilizes an applied electric field to stabilize against forces resulting from pulling the substrate through the surface of a nanoelement suspension. The electric field contours emanating from a conductive layer in the substrate, covered by an insulating layer, are modified by a patterned photoresist layer, resulting in an increased driving force for nanoelements to migrate from a liquid suspension to voids on a patterned substrate having a non-conductive surface. The method can be used for the production of microscale and nanoscale circuits, sensors, and other electronic devices.Type: ApplicationFiled: March 19, 2019Publication date: July 11, 2019Inventors: Asli Sirman, Ahmed Busnaina, Cihan Yilmaz, Jun Huang, Sivasubramanian Somu
-
Patent number: 10233559Abstract: A method for high rate assembly of nanoelements into two-dimensional void patterns on a non-conductive substrate surface utilizes an applied electric field to stabilize against forces resulting from pulling the substrate through the surface of a nanoelement suspension. The electric field contours emanating from a conductive layer in the substrate, covered by an insulating layer, are modified by a patterned photoresist layer, resulting in an increased driving force for nanoelements to migrate from a liquid suspension to voids on a patterned substrate having a non-conductive surface. The method can be used for the production of microscale and nanoscale circuits, sensors, and other electronic devices.Type: GrantFiled: November 14, 2016Date of Patent: March 19, 2019Assignee: Northeastern UniversityInventors: Asli Sirman, Ahmed Busnaina, Cihan Yilmaz, Jun Huang, Sivasubramanian Somu
-
Patent number: 10192791Abstract: A method of forming a robust low-k sidewall spacer by exposing an upper portion of the spacer to a thermal and plasma treatment prior to downstream processes and resulting device are provided. Embodiments include providing a pair of gates separated by a canyon trench over a substrate, an EPI layer in a bottom of the canyon trench, respectively, and a low-k spacer on each opposing sidewall of the pair; forming a masking layer in a bottom portion of the canyon trench, an upper portion of the low-k spacers exposed; and treating the upper portion of the low-k spacers with a thermal and plasma treatment.Type: GrantFiled: March 6, 2018Date of Patent: January 29, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Man Gu, Tao Han, Junsic Hong, Jiehui Shu, Asli Sirman, Charlotte Adams, Jinping Liu, Keith Tabakman
-
Publication number: 20170058422Abstract: A method for high rate assembly of nanoelements into two-dimensional void patterns on a non-conductive substrate surface utilizes an applied electric field to stabilize against forces resulting from pulling the substrate through the surface of a nanoelement suspension. The electric field contours emanating from a conductive layer in the substrate, covered by an insulating layer, are modified by a patterned photoresist layer, resulting in an increased driving force for nanoelements to migrate from a liquid suspension to voids on a patterned substrate having a non-conductive surface. The method can be used for the production of microscale and nanoscale circuits, sensors, and other electronic devices.Type: ApplicationFiled: November 14, 2016Publication date: March 2, 2017Inventors: Asli Sirman, Ahmed Busnaina, Cihan Yilmaz, Jun Huang, Sivasubramanian Somu
-
Patent number: 9497855Abstract: A method for high rate assembly of nanoelements into two-dimensional void patterns on a non-conductive substrate surface utilizes an applied electric field to stabilize against forces resulting from pulling the substrate through the surface of a nanoelement suspension. The electric field contours emanating from a conductive layer in the substrate, covered by an insulating layer, are modified by a patterned photoresist layer, resulting in an increased driving force for nanoelements to migrate from a liquid suspension to voids on a patterned substrate having a non-conductive surface. The method can be used for the production of microscale and nanoscale circuits, sensors, and other electronic devices.Type: GrantFiled: August 28, 2015Date of Patent: November 15, 2016Assignee: Northeastern UniversityInventors: Asli Sirman, Ahmed Busnaina, Cihan Yilmaz, Jun Huang, Sivasubramanian Somu
-
Publication number: 20160021738Abstract: A method for high rate assembly of nanoelements into two-dimensional void patterns on a non-conductive substrate surface utilizes an applied electric field to stabilize against forces resulting from pulling the substrate through the surface of a nanoelement suspension. The electric field contours emanating from a conductive layer in the substrate, covered by an insulating layer, are modified by a patterned photoresist layer, resulting in an increased driving force for nanoelements to migrate from a liquid suspension to voids on a patterned substrate having a non-conductive surface. The method can be used for the production of microscale and nanoscale circuits, sensors, and other electronic devices.Type: ApplicationFiled: August 28, 2015Publication date: January 21, 2016Inventors: Asli Sirman, Ahmed Busnaina, Cihan Yilmaz, Jun Huang, Sivasubramanian Somu
-
Patent number: 9145618Abstract: A method for high rate assembly of nanoelements into two-dimensional void patterns on a non-conductive substrate surface utilizes an applied electric field to stabilize against forces resulting from pulling the substrate through the surface of a nanoelement suspension. The electric field contours emanating from a conductive layer in the substrate, covered by an insulating layer, are modified by a patterned photoresist layer, resulting in an increased driving force for nanoelements to migrate from a liquid suspension to voids on a patterned substrate having a non-conductive surface. The method can be used for the production of microscale and nanoscale circuits, sensors, and other electronic devices.Type: GrantFiled: November 29, 2011Date of Patent: September 29, 2015Assignee: Northeastern UniversityInventors: Asli Sirman, Ahmed Busnaina, Cihan Yilmaz, Jun Huang, Sivasubramanian Somu
-
Publication number: 20130256013Abstract: A method for high rate assembly of nanoelements into two-dimensional void patterns on a non-conductive substrate surface utilizes an applied electric field to stabilize against forces resulting from pulling the substrate through the surface of a nanoelement suspension. The electric field contours emanating from a conductive layer in the substrate, covered by an insulating layer, are modified by a patterned photoresist layer, resulting in an increased driving force for nanoelements to migrate from a liquid suspension to voids on a patterned substrate having a non-conductive surface. The method can be used for the production of micro scale and nanoscale circuits, sensors, and other electronic devices.Type: ApplicationFiled: November 29, 2011Publication date: October 3, 2013Applicant: NORTHEASTERN UNIVERSITYInventors: Asli Sirman, Ahmed Busnaina, Cihan Yilmaz, Jun Huang, Sivasubramanian Somu