Patents by Inventor Asri Yusof

Asri Yusof has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9368423
    Abstract: A semiconductor device has a substrate including a base and a plurality of conductive posts extending from the base. A semiconductor die is disposed on a surface of the base between the conductive posts. An interconnect structure is formed over the semiconductor die and conductive posts. An adhesive layer is disposed over the semiconductor die. A conductive layer is disposed over the adhesive layer. An encapsulant is deposited over the semiconductor die and around the conductive posts. One or more conductive posts are electrically isolated from the substrate. The conductive layer is a removable or sacrificial cap layer. The substrate includes a wafer-shape, panel, or singulated form. The semiconductor die is disposed below a height of the conductive posts. An interconnect structure is formed over the semiconductor die, encapsulant, and conductive posts.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: June 14, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Tai Do, Arnel Trasporto, Linda Pei Ee Chua, Asri Yusof
  • Patent number: 9190349
    Abstract: An integrated circuit packaging system and method of manufacture thereof including: providing an unplated leadframe having a contact protrusion; depositing a solder resist on the contact protrusion; forming a contact pad and traces by etching the unplated leadframe; applying a trace protection layer on the contact pad and the traces; removing the solder resist; forming a recess in the trace protection layer by etching a top surface of the contact pad to a recess distance below a top surface of the trace protection layer; and depositing an external connector directly on the top surface of the contact pad.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: November 17, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua, Asri Yusof
  • Patent number: 9142530
    Abstract: A system and method for manufacturing an integrated circuit packaging system includes: forming a base substrate including: providing a sacrificial carrier: mounting a metallic sheet on the sacrificial carrier, applying a top trace to the metallic sheet, forming a conductive stud on the top trace, forming a base encapsulation over the metallic sheet, the top trace, and the conductive stud, the top trace exposed from a top surface of the base encapsulation, and removing the sacrificial carrier and the metallic sheet; mounting an integrated circuit device on the base substrate; and encapsulating the integrated circuit device and the base substrate with a top encapsulation.
    Type: Grant
    Filed: March 15, 2014
    Date of Patent: September 22, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Sung Soo Kim, Asri Yusof, In Sang Yoon
  • Patent number: 9105620
    Abstract: A system and method of manufacture of an integrated circuit packaging system includes: a leadframe with a conductive layer on a leadframe active side for protecting a lead pad and a routable trace, the leadframe having an overmold recess at a leadframe inactive side; an overmold layer in the overmold recess, the overmold layer exposed between the lead pad and the routable trace for forming the lead pad and routable trace; an encapsulation directly on the conductive layer, the lead pad, the routable trace, and the overmold layer; and an external interconnect at the leadframe inactive side.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: August 11, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Linda Pei Ee Chua, Asri Yusof
  • Patent number: 8937379
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a leadframe having a trench; mounting an integrated circuit device on the leadframe; forming a top encapsulation on the leadframe and the trench; forming a lead having a lead protrusion and a peripheral groove, the lead protrusion and the peripheral groove formed from etching the trench at a leadframe bottom side; and forming a bottom encapsulation surrounding a lead bottom side of the lead.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: January 20, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Asri Yusof, Arnel Senosa Trasporto, Linda Pei Ee Chua
  • Publication number: 20150001707
    Abstract: A semiconductor device has a substrate including a base and a plurality of conductive posts extending from the base. A semiconductor die is disposed on a surface of the base between the conductive posts. An interconnect structure is formed over the semiconductor die and conductive posts. An adhesive layer is disposed over the semiconductor die. A conductive layer is disposed over the adhesive layer. An encapsulant is deposited over the semiconductor die and around the conductive posts. One or more conductive posts are electrically isolated from the substrate. The conductive layer is a removable or sacrificial cap layer. The substrate includes a wafer-shape, panel, or singulated form. The semiconductor die is disposed below a height of the conductive posts. An interconnect structure is formed over the semiconductor die, encapsulant, and conductive posts.
    Type: Application
    Filed: June 28, 2013
    Publication date: January 1, 2015
    Inventors: Byung Tai Do, Arnel Trasporto, Linda Pei Ee Chua, Asri Yusof
  • Publication number: 20140284791
    Abstract: A system and method for manufacturing an integrated circuit packaging system includes: forming a base substrate including: providing a sacrificial carrier: mounting a metallic sheet on the sacrificial carrier, applying a top trace to the metallic sheet, forming a conductive stud on the top trace, forming a base encapsulation over the metallic sheet, the top trace, and the conductive stud, the top trace exposed from a top surface of the base encapsulation, and removing the sacrificial carrier and the metallic sheet; mounting an integrated circuit device on the base substrate; and encapsulating the integrated circuit device and the base substrate with a top encapsulation.
    Type: Application
    Filed: March 15, 2014
    Publication date: September 25, 2014
    Inventors: Byung Tai Do, Arnel Senosa Trasporto, Sung Soo Kim, Asri Yusof, In Sang Yoon
  • Patent number: 8210459
    Abstract: A wire winder includes a body configured to anchor a wire and such that the wire extends from the body. The body is at least partially surrounded by a rotatable bobbin journalled on the body. The wire is windable onto the body within the rotatable bobbin from a direction substantially aligned with a bobbin axis. The bobbin rotation is indexed by coaction between at least one projection or depression on the body and at least one depression or projection on the bobbin.
    Type: Grant
    Filed: August 30, 2007
    Date of Patent: July 3, 2012
    Assignees: Sony EMCS (Malaysia) Sdn. Bhd., Sony Corporation
    Inventors: Mohd Asri Yusof, Yuen Chang Chuah, Toshihide Ooba
  • Publication number: 20080128544
    Abstract: A wire winder includes a body configured to anchor a wire and such that the wire extends from the body. The body is at least partially surrounded by a rotatable bobbin journalled on the body. The wire is windable onto the body within the rotatable bobbin from a direction substantially aligned with a bobbin axis. The bobbin rotation is indexed by coaction between at least one projection or depression on the body and at least one depression or projection on the bobbin.
    Type: Application
    Filed: August 30, 2007
    Publication date: June 5, 2008
    Applicants: Sony Corporation, sony EMCS (Malaysia) Sdn. Bhd.
    Inventors: Mohd Asri YUSOF, Yuen Chang Chuah, Toshihide Ooba