Abstract: An integrated circuit device comprising one or more data processing circuits, each having an input stage, a combinatorial logic stage and an output stage. The input stage is responsive to a clock signal, and receives at least a first and second set of data signals and provides the first set to an input of the logic stage during a first portion of a clock signal period, and provides the second set to the input during a second portion of the period. The output stage is responsive to the clock signal, and receives from an output of the logic stage at least a first result signal as a function of the first set during a first portion of a subsequent clock signal period and receives from the output at least a second result signal as a function of the second set during a second portion of the subsequent period.

Abstract: An integrated circuit device comprising one or more data processing circuits is provided, where each data processing circuit has an input stage, a combinatorial logic stage and an output stage. The input stage is responsive to a clock signal, and receives at least a first and a second set of data signals and provides the first set of data signals to an input of the combinatorial logic stage during a first portion of a period of the clock signal, and provides the second set of data signals to the input during a second portion of the period. The output stage is responsive to the clock signal, and receives from an output of the combinatorial logic stage at least a first result signal as a function of the first set of data signals during a first portion of a subsequent period of the clock signal and receive from the output at least a second result signal as a function of the second set of data signals during a second portion of the subsequent period.

Abstract: A method for evaluating a dynamic power consumption of a block, the method includes: receiving or generating information representative of the block during a preliminary block design stage that precedes a gate level simulation of the block; estimating change probabilities of signals of internal components of the block; and evaluating a dynamic power consumption of the block in response to the change probabilities of the signals of internal components of the block.

Abstract: A method for evaluating a dynamic power consumption of a block, the method includes: receiving or generating information representative of the block during a preliminary block design stage that precedes a gate level simulation of the block; estimating change probabilities of signals of internal components of the block; and evaluating a dynamic power consumption of the block in response to the change probabilities of the signals of internal components of the block.